| Message ID | 1546955444-7549-4-git-send-email-jianxin.pan@amlogic.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: meson: add a sub EMMC clock controller support | expand |
On Tue, 2019-01-08 at 21:50 +0800, Jianxin Pan wrote: > From: Yixun Lan <yixun.lan@amlogic.com> > > Document the MMC sub clock controller driver, the potential consumer > of this driver is MMC or NAND. Also add four clock bindings IDs which > provided by this driver. > > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> > Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com> > --- > .../devicetree/bindings/clock/amlogic,mmc-clkc.txt | 39 > ++++++++++++++++++++++ > include/dt-bindings/clock/amlogic,mmc-clkc.h | 17 ++++++++++ > 2 files changed, 56 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc- > clkc.txt > create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h > > diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt > b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt > new file mode 100644 > index 0000000..0f518e6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt > @@ -0,0 +1,39 @@ > +* Amlogic MMC Sub Clock Controller Driver > + > +The Amlogic MMC clock controller generates and supplies clock to support > +MMC and NAND controller > + > +Required Properties: > + > +- compatible: should be: > + "amlogic,gx-mmc-clkc" > + "amlogic,axg-mmc-clkc" nitpick, missing is something to tell that only one is required, not both for example `should be one of the following` > + > +- #clock-cells: should be 1. > +- clocks: phandles to clocks corresponding to the clock-names property > +- clock-names: list of parent clock names > + - "clkin0", "clkin1" > + > +- reg: address of emmc sub clock register > + > +Example: Clock controller node: > + > +sd_mmc_c_clkc: clock-controller@7000 { > + compatible = "amlogic,axg-mmc-clkc", "syscon"; > + reg = <0x0 0x7000 0x0 0x4>; > + #clock-cells = <1>; > + > + clock-names = "clkin0", "clkin1"; > + clocks = <&clkc CLKID_SD_MMC_C_CLK0>, > + <&clkc CLKID_FCLK_DIV2>; > +}; > + > +sd_emmc_b_clkc: clock-controller@5000 { > + compatible = "amlogic,axg-mmc-clkc", "syscon"; > + reg = <0x0 0x5000 0x0 0x4>; > + > + #clock-cells = <1>; > + clock-names = "clkin0", "clkin1"; > + clocks = <&clkc CLKID_SD_EMMC_B_CLK0>, > + <&clkc CLKID_FCLK_DIV2>; > +}; > diff --git a/include/dt-bindings/clock/amlogic,mmc-clkc.h b/include/dt- > bindings/clock/amlogic,mmc-clkc.h > new file mode 100644 > index 0000000..34a3c56 > --- /dev/null > +++ b/include/dt-bindings/clock/amlogic,mmc-clkc.h > @@ -0,0 +1,17 @@ > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ > +/* > + * Meson MMC sub clock tree IDs > + * > + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. > + * Author: Yixun Lan <yixun.lan@amlogic.com> > + */ > + > +#ifndef __MMC_CLKC_H > +#define __MMC_CLKC_H > + > +#define CLKID_MMC_DIV 0 > +#define CLKID_MMC_PHASE_CORE 1 > +#define CLKID_MMC_PHASE_TX 2 > +#define CLKID_MMC_PHASE_RX 3 > + > +#endif
diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt new file mode 100644 index 0000000..0f518e6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt @@ -0,0 +1,39 @@ +* Amlogic MMC Sub Clock Controller Driver + +The Amlogic MMC clock controller generates and supplies clock to support +MMC and NAND controller + +Required Properties: + +- compatible: should be: + "amlogic,gx-mmc-clkc" + "amlogic,axg-mmc-clkc" + +- #clock-cells: should be 1. +- clocks: phandles to clocks corresponding to the clock-names property +- clock-names: list of parent clock names + - "clkin0", "clkin1" + +- reg: address of emmc sub clock register + +Example: Clock controller node: + +sd_mmc_c_clkc: clock-controller@7000 { + compatible = "amlogic,axg-mmc-clkc", "syscon"; + reg = <0x0 0x7000 0x0 0x4>; + #clock-cells = <1>; + + clock-names = "clkin0", "clkin1"; + clocks = <&clkc CLKID_SD_MMC_C_CLK0>, + <&clkc CLKID_FCLK_DIV2>; +}; + +sd_emmc_b_clkc: clock-controller@5000 { + compatible = "amlogic,axg-mmc-clkc", "syscon"; + reg = <0x0 0x5000 0x0 0x4>; + + #clock-cells = <1>; + clock-names = "clkin0", "clkin1"; + clocks = <&clkc CLKID_SD_EMMC_B_CLK0>, + <&clkc CLKID_FCLK_DIV2>; +}; diff --git a/include/dt-bindings/clock/amlogic,mmc-clkc.h b/include/dt-bindings/clock/amlogic,mmc-clkc.h new file mode 100644 index 0000000..34a3c56 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,mmc-clkc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Meson MMC sub clock tree IDs + * + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + * Author: Yixun Lan <yixun.lan@amlogic.com> + */ + +#ifndef __MMC_CLKC_H +#define __MMC_CLKC_H + +#define CLKID_MMC_DIV 0 +#define CLKID_MMC_PHASE_CORE 1 +#define CLKID_MMC_PHASE_TX 2 +#define CLKID_MMC_PHASE_RX 3 + +#endif