diff mbox series

[PATCH/RFT] arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices

Message ID 1547553762-4467-1-git-send-email-ykaneko0929@gmail.com (mailing list archive)
State Accepted
Commit dd7188eb4ed128dccc16b1d7dc1d639ddbd8882a
Delegated to: Simon Horman
Headers show
Series [PATCH/RFT] arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices | expand

Commit Message

Yoshihiro Kaneko Jan. 15, 2019, 12:02 p.m. UTC 
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>

This patch define OOP tables for all CPUs.
This allows CPUFreq to function.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
---

This patch is based on the devel branch of Simon Horman's renesas tree.

 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

Comments

Simon Horman Jan. 28, 2019, 2:05 p.m. UTC | #1 
On Tue, Jan 15, 2019 at 09:02:42PM +0900, Yoshihiro Kaneko wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> 
> This patch define OOP tables for all CPUs.
> This allows CPUFreq to function.
> 
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> ---

Thanks, I have tested CPUFreq with this tested that with this patch and
"[PATCH] clk: renesas: r8a77990: Add Z2 clock"
(https://patchwork.kernel.org/patch/10783723/) applied on top of
renesas-devel-20190128-v5.0-rc4.

Geert, or others, is it expected that z2 does not scale
in this test?

# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor 
performance
# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
800000 1000000 1200000 
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1200000
/sys/kernel/debug/clk/z2/clk_rate:1200000000
# echo 1000000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1000000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1000000
/sys/kernel/debug/clk/z2/clk_rate:1200000000
# echo 1000000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1000000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1000000
/sys/kernel/debug/clk/z2/clk_rate:1200000000
# echo 800000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:800000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:800000
/sys/kernel/debug/clk/z2/clk_rate:1200000000
# echo 1200000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1200000
/sys/kernel/debug/clk/z2/clk_rate:1200000000

> 
> This patch is based on the devel branch of Simon Horman's renesas tree.
> 
>  arch/arm64/boot/dts/renesas/r8a77990.dtsi | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> index 84bbe70..936714e 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> @@ -55,6 +55,27 @@
>  		clock-frequency = <0>;
>  	};
>  
> +	cluster1_opp: opp_table10 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +		opp-800000000 {
> +			opp-hz = /bits/ 64 <800000000>;
> +			opp-microvolt = <820000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp-1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <820000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp-1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <820000>;
> +			clock-latency-ns = <300000>;
> +			opp-suspend;
> +		};
> +	};
> +
>  	cpus {
>  		#address-cells = <1>;
>  		#size-cells = <0>;
> @@ -66,6 +87,8 @@
>  			power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
>  			next-level-cache = <&L2_CA53>;
>  			enable-method = "psci";
> +			clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
> +			operating-points-v2 = <&cluster1_opp>;
>  		};
>  
>  		a53_1: cpu@1 {
> @@ -75,6 +98,8 @@
>  			power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
>  			next-level-cache = <&L2_CA53>;
>  			enable-method = "psci";
> +			clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
> +			operating-points-v2 = <&cluster1_opp>;
>  		};
>  
>  		L2_CA53: cache-controller-0 {
> -- 
> 1.9.1
>
Geert Uytterhoeven Jan. 28, 2019, 3:15 p.m. UTC | #2 
Hi Simon,

On Mon, Jan 28, 2019 at 3:05 PM Simon Horman <horms@verge.net.au> wrote:
> On Tue, Jan 15, 2019 at 09:02:42PM +0900, Yoshihiro Kaneko wrote:
> > From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> >
> > This patch define OOP tables for all CPUs.
> > This allows CPUFreq to function.
> >
> > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> > ---
>
> Thanks, I have tested CPUFreq with this tested that with this patch and
> "[PATCH] clk: renesas: r8a77990: Add Z2 clock"
> (https://patchwork.kernel.org/patch/10783723/) applied on top of
> renesas-devel-20190128-v5.0-rc4.
>
> Geert, or others, is it expected that z2 does not scale
> in this test?

Given your patch adds the Z2 clock as a fixed clock, this is expected ;-)

Note that the BSP adds this clock as a programmable clock of type
CLK_TYPE_GEN3_Z2.

Gr{oetje,eeting}s,

                        Geert
Simon Horman Jan. 28, 2019, 4:36 p.m. UTC | #3 
On Mon, Jan 28, 2019 at 04:15:30PM +0100, Geert Uytterhoeven wrote:
> Hi Simon,
> 
> On Mon, Jan 28, 2019 at 3:05 PM Simon Horman <horms@verge.net.au> wrote:
> > On Tue, Jan 15, 2019 at 09:02:42PM +0900, Yoshihiro Kaneko wrote:
> > > From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > >
> > > This patch define OOP tables for all CPUs.
> > > This allows CPUFreq to function.
> > >
> > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > > Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> > > ---
> >
> > Thanks, I have tested CPUFreq with this tested that with this patch and
> > "[PATCH] clk: renesas: r8a77990: Add Z2 clock"
> > (https://patchwork.kernel.org/patch/10783723/) applied on top of
> > renesas-devel-20190128-v5.0-rc4.
> >
> > Geert, or others, is it expected that z2 does not scale
> > in this test?
> 
> Given your patch adds the Z2 clock as a fixed clock, this is expected ;-)
> 
> Note that the BSP adds this clock as a programmable clock of type
> CLK_TYPE_GEN3_Z2.

Thanks, understood.
Simon Horman Jan. 30, 2019, 9:46 a.m. UTC | #4 
On Mon, Jan 28, 2019 at 05:36:39PM +0100, Simon Horman wrote:
> On Mon, Jan 28, 2019 at 04:15:30PM +0100, Geert Uytterhoeven wrote:
> > Hi Simon,
> > 
> > On Mon, Jan 28, 2019 at 3:05 PM Simon Horman <horms@verge.net.au> wrote:
> > > On Tue, Jan 15, 2019 at 09:02:42PM +0900, Yoshihiro Kaneko wrote:
> > > > From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > > >
> > > > This patch define OOP tables for all CPUs.
> > > > This allows CPUFreq to function.
> > > >
> > > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > > > Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> > > > ---
> > >
> > > Thanks, I have tested CPUFreq with this tested that with this patch and
> > > "[PATCH] clk: renesas: r8a77990: Add Z2 clock"
> > > (https://patchwork.kernel.org/patch/10783723/) applied on top of
> > > renesas-devel-20190128-v5.0-rc4.
> > >
> > > Geert, or others, is it expected that z2 does not scale
> > > in this test?
> > 
> > Given your patch adds the Z2 clock as a fixed clock, this is expected ;-)
> > 
> > Note that the BSP adds this clock as a programmable clock of type
> > CLK_TYPE_GEN3_Z2.
> 
> Thanks, understood.

I have now tested this patch in conjunction with
"[PATCH v2 0/6] clk: renesas: r8a77990: Add Z2 clock" [1],
which implements Z2 as a variable clock, and the results
seem substantially better.

# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
performance
# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
800000 1000000 1200000 
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1200000
/sys/kernel/debug/clk/z2/clk_rate:1200000000

# echo 1000000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:975000
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1000000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:975000
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1000000
/sys/kernel/debug/clk/z2/clk_rate:975000000

# echo 800000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
# grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:787500
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:800000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:787500
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:800000
/sys/kernel/debug/clk/z2/clk_rate:787500000

# echo 1200000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq
# /sys/kernel/debug/clk/z2/clk_rate
/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1200000
/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000
/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1200000
/sys/kernel/debug/clk/z2/clk_rate:1200000000

Tested-by: Simon Horman <horms+renesas@verge.net.au>

[1] https://lore.kernel.org/linux-renesas-soc/20190130094029.9604-1-horms+renesas@verge.net.au/T/#mec59a349508e0be00d3a1d6ef89f838c0e193591
Simon Horman Feb. 5, 2019, 2:43 p.m. UTC | #5 
On Wed, Jan 30, 2019 at 10:46:12AM +0100, Simon Horman wrote:
> On Mon, Jan 28, 2019 at 05:36:39PM +0100, Simon Horman wrote:
> > On Mon, Jan 28, 2019 at 04:15:30PM +0100, Geert Uytterhoeven wrote:
> > > Hi Simon,
> > > 
> > > On Mon, Jan 28, 2019 at 3:05 PM Simon Horman <horms@verge.net.au> wrote:
> > > > On Tue, Jan 15, 2019 at 09:02:42PM +0900, Yoshihiro Kaneko wrote:
> > > > > From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > > > >
> > > > > This patch define OOP tables for all CPUs.
> > > > > This allows CPUFreq to function.
> > > > >
> > > > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > > > > Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> > > > > ---
> > > >
> > > > Thanks, I have tested CPUFreq with this tested that with this patch and
> > > > "[PATCH] clk: renesas: r8a77990: Add Z2 clock"
> > > > (https://patchwork.kernel.org/patch/10783723/) applied on top of
> > > > renesas-devel-20190128-v5.0-rc4.
> > > >
> > > > Geert, or others, is it expected that z2 does not scale
> > > > in this test?
> > > 
> > > Given your patch adds the Z2 clock as a fixed clock, this is expected ;-)
> > > 
> > > Note that the BSP adds this clock as a programmable clock of type
> > > CLK_TYPE_GEN3_Z2.
> > 
> > Thanks, understood.
> 
> I have now tested this patch in conjunction with
> "[PATCH v2 0/6] clk: renesas: r8a77990: Add Z2 clock" [1],
> which implements Z2 as a variable clock, and the results
> seem substantially better.

With the above in mind I have applied this patch for v5.1.

> 
> # cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
> performance
> # cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
> 800000 1000000 1200000 
> # grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate
> /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000
> /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1200000
> /sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000
> /sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1200000
> /sys/kernel/debug/clk/z2/clk_rate:1200000000
> 
> # echo 1000000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
> # grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate
> /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:975000
> /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1000000
> /sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:975000
> /sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1000000
> /sys/kernel/debug/clk/z2/clk_rate:975000000
> 
> # echo 800000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
> # grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate
> /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:787500
> /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:800000
> /sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:787500
> /sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:800000
> /sys/kernel/debug/clk/z2/clk_rate:787500000
> 
> # echo 1200000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq
> # /sys/kernel/debug/clk/z2/clk_rate
> /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000
> /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1200000
> /sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000
> /sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1200000
> /sys/kernel/debug/clk/z2/clk_rate:1200000000
> 
> Tested-by: Simon Horman <horms+renesas@verge.net.au>
> 
> [1] https://lore.kernel.org/linux-renesas-soc/20190130094029.9604-1-horms+renesas@verge.net.au/T/#mec59a349508e0be00d3a1d6ef89f838c0e193591
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 84bbe70..936714e 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -55,6 +55,27 @@ 
 		clock-frequency = <0>;
 	};
 
+	cluster1_opp: opp_table10 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <820000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <820000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <820000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -66,6 +87,8 @@ 
 			power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
+			operating-points-v2 = <&cluster1_opp>;
 		};
 
 		a53_1: cpu@1 {
@@ -75,6 +98,8 @@ 
 			power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
+			operating-points-v2 = <&cluster1_opp>;
 		};
 
 		L2_CA53: cache-controller-0 {