diff mbox series

[v4.1,3/3] drm/i915/gen9+: Add support for pipe background color (v4)

Message ID 20190130185122.10322-4-matthew.d.roper@intel.com (mailing list archive)
State New, archived
Headers show
Series CRTC background color | expand

Commit Message

Matt Roper Jan. 30, 2019, 6:51 p.m. UTC 
Gen9+ platforms allow CRTC's to be programmed with a background/canvas
color below the programmable planes.  Let's expose this for use by
compositors.

v2:
 - Split out bgcolor sanitization and programming of csc/gamma bits to a
   separate patch that we can land before the ABI changes are ready to
   go in.  (Ville)
 - Change a temporary variable name to be more consistent with
   other similar functions.  (Ville)
 - Change register name to SKL_CANVAS for consistency with the
   CHV_CANVAS register.

v3:
 - Switch register name back to SKL_BOTTOM_COLOR.  (Ville)
 - Use non-_FW register write.  (Ville)
 - Minor parameter rename for consistency.  (Ville)

v4:
 - Removed use of bgcolor_changed flag.

Cc: dri-devel@lists.freedesktop.org
Cc: wei.c.li@intel.com
Cc: harish.krupo.kps@intel.com
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  9 +++++++
 drivers/gpu/drm/i915/intel_display.c | 46 +++++++++++++++++++++++++++---------
 2 files changed, 44 insertions(+), 11 deletions(-)

Comments

Ville Syrjälä Jan. 30, 2019, 9:08 p.m. UTC | #1 
On Wed, Jan 30, 2019 at 10:51:22AM -0800, Matt Roper wrote:
> Gen9+ platforms allow CRTC's to be programmed with a background/canvas
> color below the programmable planes.  Let's expose this for use by
> compositors.
> 
> v2:
>  - Split out bgcolor sanitization and programming of csc/gamma bits to a
>    separate patch that we can land before the ABI changes are ready to
>    go in.  (Ville)
>  - Change a temporary variable name to be more consistent with
>    other similar functions.  (Ville)
>  - Change register name to SKL_CANVAS for consistency with the
>    CHV_CANVAS register.
> 
> v3:
>  - Switch register name back to SKL_BOTTOM_COLOR.  (Ville)
>  - Use non-_FW register write.  (Ville)
>  - Minor parameter rename for consistency.  (Ville)
> 
> v4:
>  - Removed use of bgcolor_changed flag.
> 
> Cc: dri-devel@lists.freedesktop.org
> Cc: wei.c.li@intel.com
> Cc: harish.krupo.kps@intel.com
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c  |  9 +++++++
>  drivers/gpu/drm/i915/intel_display.c | 46 +++++++++++++++++++++++++++---------
>  2 files changed, 44 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index fa2c226fc779..8b07dd05c54e 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3092,6 +3092,15 @@ static int i915_display_info(struct seq_file *m, void *unused)
>  			intel_plane_info(m, crtc);
>  		}
>  
> +		if (INTEL_GEN(dev_priv) >= 9 && pipe_config->base.active) {
> +			uint64_t background = pipe_config->base.bgcolor;
> +
> +			seq_printf(m, "\tbackground color (10bpc): r=%x g=%x b=%x\n",
> +				   DRM_ARGB_RED(background, 10),
> +				   DRM_ARGB_GREEN(background, 10),
> +				   DRM_ARGB_BLUE(background, 10));
> +		}
> +
>  		seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
>  			   yesno(!crtc->cpu_fifo_underrun_disabled),
>  			   yesno(!crtc->pch_fifo_underrun_disabled));
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a025efb1d7c6..bc78743e1411 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3896,6 +3896,28 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
>  	clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
>  }
>  
> +static void
> +skl_update_background_color(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	uint64_t propval = crtc_state->base.bgcolor;
> +	uint32_t tmp;
> +
> +	/* Hardware is programmed with 10 bits of precision */
> +	tmp = DRM_ARGB_RED(propval, 10) << 20
> +	    | DRM_ARGB_GREEN(propval, 10) << 10
> +	    | DRM_ARGB_BLUE(propval, 10);
> +
> +	/*
> +	 * Set CSC and gamma for bottom color to ensure background pixels
> +	 * receive the same color transformations as plane content.
> +	 */
> +	tmp |= SKL_BOTTOM_COLOR_CSC_ENABLE | SKL_BOTTOM_COLOR_GAMMA_ENABLE;
> +
> +	I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe), tmp);
> +}

Readout + state check would be nice too.

Anyways
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +
>  static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
>  				     const struct intel_crtc_state *new_crtc_state)
>  {
> @@ -3931,15 +3953,8 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta
>  			ironlake_pfit_disable(old_crtc_state);
>  	}
>  
> -	/*
> -	 * We don't (yet) allow userspace to control the pipe background color,
> -	 * so force it to black, but apply pipe gamma and CSC so that its
> -	 * handling will match how we program our planes.
> -	 */
>  	if (INTEL_GEN(dev_priv) >= 9)
> -		I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
> -			   SKL_BOTTOM_COLOR_GAMMA_ENABLE |
> -			   SKL_BOTTOM_COLOR_CSC_ENABLE);
> +		skl_update_background_color(new_crtc_state);
>  }
>  
>  static void intel_fdi_normal_train(struct intel_crtc *crtc)
> @@ -11042,6 +11057,8 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_crtc_state *pipe_config =
>  		to_intel_crtc_state(crtc_state);
> +	struct drm_crtc_state *old_crtc_state =
> +		drm_atomic_get_old_crtc_state(crtc_state->state, crtc);
>  	int ret;
>  	bool mode_changed = needs_modeset(crtc_state);
>  
> @@ -11069,6 +11086,9 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
>  		crtc_state->planes_changed = true;
>  	}
>  
> +	if (crtc_state->bgcolor != old_crtc_state->bgcolor)
> +		pipe_config->update_pipe = true;
> +
>  	ret = 0;
>  	if (dev_priv->display.compute_pipe_wm) {
>  		ret = dev_priv->display.compute_pipe_wm(pipe_config);
> @@ -14238,6 +14258,9 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
>  
>  	WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
>  
> +	if (INTEL_GEN(dev_priv) >= 9)
> +		drm_crtc_add_bgcolor_property(&intel_crtc->base);
> +
>  	return 0;
>  
>  fail:
> @@ -15478,6 +15501,9 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
>  	struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  
> +	/* Always force bgcolor to solid black */
> +	crtc_state->base.bgcolor = drm_argb(16, 0xFFFF, 0, 0, 0);
> +
>  	/* Clear any frame start delays used for debugging left by the BIOS */
>  	if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
>  		i915_reg_t reg = PIPECONF(cpu_transcoder);
> @@ -15504,9 +15530,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
>  		 * gamma and CSC to match how we program our planes.
>  		 */
>  		if (INTEL_GEN(dev_priv) >= 9)
> -			I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
> -				   SKL_BOTTOM_COLOR_GAMMA_ENABLE |
> -				   SKL_BOTTOM_COLOR_CSC_ENABLE);
> +			skl_update_background_color(crtc_state);
>  	}
>  
>  	/* Adjust the state of the output pipe according to whether we
> -- 
> 2.14.5
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fa2c226fc779..8b07dd05c54e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3092,6 +3092,15 @@  static int i915_display_info(struct seq_file *m, void *unused)
 			intel_plane_info(m, crtc);
 		}
 
+		if (INTEL_GEN(dev_priv) >= 9 && pipe_config->base.active) {
+			uint64_t background = pipe_config->base.bgcolor;
+
+			seq_printf(m, "\tbackground color (10bpc): r=%x g=%x b=%x\n",
+				   DRM_ARGB_RED(background, 10),
+				   DRM_ARGB_GREEN(background, 10),
+				   DRM_ARGB_BLUE(background, 10));
+		}
+
 		seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
 			   yesno(!crtc->cpu_fifo_underrun_disabled),
 			   yesno(!crtc->pch_fifo_underrun_disabled));
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a025efb1d7c6..bc78743e1411 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3896,6 +3896,28 @@  void intel_finish_reset(struct drm_i915_private *dev_priv)
 	clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
 }
 
+static void
+skl_update_background_color(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	uint64_t propval = crtc_state->base.bgcolor;
+	uint32_t tmp;
+
+	/* Hardware is programmed with 10 bits of precision */
+	tmp = DRM_ARGB_RED(propval, 10) << 20
+	    | DRM_ARGB_GREEN(propval, 10) << 10
+	    | DRM_ARGB_BLUE(propval, 10);
+
+	/*
+	 * Set CSC and gamma for bottom color to ensure background pixels
+	 * receive the same color transformations as plane content.
+	 */
+	tmp |= SKL_BOTTOM_COLOR_CSC_ENABLE | SKL_BOTTOM_COLOR_GAMMA_ENABLE;
+
+	I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe), tmp);
+}
+
 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
 				     const struct intel_crtc_state *new_crtc_state)
 {
@@ -3931,15 +3953,8 @@  static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta
 			ironlake_pfit_disable(old_crtc_state);
 	}
 
-	/*
-	 * We don't (yet) allow userspace to control the pipe background color,
-	 * so force it to black, but apply pipe gamma and CSC so that its
-	 * handling will match how we program our planes.
-	 */
 	if (INTEL_GEN(dev_priv) >= 9)
-		I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
-			   SKL_BOTTOM_COLOR_GAMMA_ENABLE |
-			   SKL_BOTTOM_COLOR_CSC_ENABLE);
+		skl_update_background_color(new_crtc_state);
 }
 
 static void intel_fdi_normal_train(struct intel_crtc *crtc)
@@ -11042,6 +11057,8 @@  static int intel_crtc_atomic_check(struct drm_crtc *crtc,
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_crtc_state *pipe_config =
 		to_intel_crtc_state(crtc_state);
+	struct drm_crtc_state *old_crtc_state =
+		drm_atomic_get_old_crtc_state(crtc_state->state, crtc);
 	int ret;
 	bool mode_changed = needs_modeset(crtc_state);
 
@@ -11069,6 +11086,9 @@  static int intel_crtc_atomic_check(struct drm_crtc *crtc,
 		crtc_state->planes_changed = true;
 	}
 
+	if (crtc_state->bgcolor != old_crtc_state->bgcolor)
+		pipe_config->update_pipe = true;
+
 	ret = 0;
 	if (dev_priv->display.compute_pipe_wm) {
 		ret = dev_priv->display.compute_pipe_wm(pipe_config);
@@ -14238,6 +14258,9 @@  static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
 
 	WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
 
+	if (INTEL_GEN(dev_priv) >= 9)
+		drm_crtc_add_bgcolor_property(&intel_crtc->base);
+
 	return 0;
 
 fail:
@@ -15478,6 +15501,9 @@  static void intel_sanitize_crtc(struct intel_crtc *crtc,
 	struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
+	/* Always force bgcolor to solid black */
+	crtc_state->base.bgcolor = drm_argb(16, 0xFFFF, 0, 0, 0);
+
 	/* Clear any frame start delays used for debugging left by the BIOS */
 	if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
 		i915_reg_t reg = PIPECONF(cpu_transcoder);
@@ -15504,9 +15530,7 @@  static void intel_sanitize_crtc(struct intel_crtc *crtc,
 		 * gamma and CSC to match how we program our planes.
 		 */
 		if (INTEL_GEN(dev_priv) >= 9)
-			I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
-				   SKL_BOTTOM_COLOR_GAMMA_ENABLE |
-				   SKL_BOTTOM_COLOR_CSC_ENABLE);
+			skl_update_background_color(crtc_state);
 	}
 
 	/* Adjust the state of the output pipe according to whether we