| Message ID | 20190131094021.3092-6-horms+renesas@verge.net.au (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | clk: renesas: r8a77990: Add Z2 clock | expand |
Hello Simon, I get the same results for the RZ/G2E on EK874: # cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies 800000 1000000 1200000 # grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000 /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1200000 /sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000 /sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1200000 /sys/kernel/debug/clk/z2/clk_rate:1200000000 # echo 1000000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq # grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:975000 /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1000000 /sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:975000 /sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1000000 /sys/kernel/debug/clk/z2/clk_rate:975000000 # echo 800000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq # grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:787500 /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:800000 /sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:787500 /sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:800000 /sys/kernel/debug/clk/z2/clk_rate:787500000 # echo 1200000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq # grep . /sys/devices/system/cpu/cpu*/cpufreq/*_cur_freq /sys/kernel/debug/clk/z2/clk_rate /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq:1200000 /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq:1200000 /sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq:1200000 /sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq:1200000 /sys/kernel/debug/clk/z2/clk_rate:1200000000 > From: Simon Horman <horms+renesas@verge.net.au> > Sent: 31 January 2019 09:40 > Subject: [PATCH/RFT v3 5/5] clk: renesas: r8a774c0: Add Z2 clock > > Adds support for R-Car RZ/G2E (r8a774c0) Z2 clock. > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Tested-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > --- > v3: New patch > --- > drivers/clk/renesas/r8a774c0-cpg-mssr.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c > index 10b96895d452..24634ca94f69 100644 > --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c > @@ -79,6 +79,7 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { > /* Core Clock Outputs */ > DEF_FIXED("za2", R8A774C0_CLK_ZA2, CLK_PLL0D24, 1, 1), > DEF_FIXED("za8", R8A774C0_CLK_ZA8, CLK_PLL0D8, 1, 1), > +DEF_GEN3_Z("z2", R8A774C0_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL0, 4, 8), > DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1), > DEF_FIXED("zt", R8A774C0_CLK_ZT, CLK_PLL1, 4, 1), > DEF_FIXED("zx", R8A774C0_CLK_ZX, CLK_PLL1, 3, 1), > -- > 2.11.0 Cheers, Fab Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
On Thu, Jan 31, 2019 at 10:40 AM Simon Horman <horms+renesas@verge.net.au> wrote: > Adds support for R-Car RZ/G2E (r8a774c0) Z2 clock. > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c index 10b96895d452..24634ca94f69 100644 --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c @@ -79,6 +79,7 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_FIXED("za2", R8A774C0_CLK_ZA2, CLK_PLL0D24, 1, 1), DEF_FIXED("za8", R8A774C0_CLK_ZA8, CLK_PLL0D8, 1, 1), + DEF_GEN3_Z("z2", R8A774C0_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL0, 4, 8), DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("zt", R8A774C0_CLK_ZT, CLK_PLL1, 4, 1), DEF_FIXED("zx", R8A774C0_CLK_ZX, CLK_PLL1, 3, 1),
Adds support for R-Car RZ/G2E (r8a774c0) Z2 clock. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- v3: New patch --- drivers/clk/renesas/r8a774c0-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+)