| Message ID | 20181229143556.27339-3-martin.blumenstingl@googlemail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Meson8b RGMII Ethernet pin fixes | expand |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes: > According to the Odroid-C1+ schematics the Ethernet TXD1 signal is > routed to GPIOH_5 and the TXD0 signal is routed to GPIOH_6. > The public S805 datasheet shows that TXD0 can be routed to DIF_2_P and > TXD1 can be routed to DIF_2_N instead. > > The pin groups eth_txd0_0 (GPIOH_6) and eth_txd0_1 (DIF_2_P) are both > configured as Ethernet TXD0 and TXD1 data lines in meson8b.dtsi. At the > same time eth_txd1_0 (GPIOH_5) and eth_txd1_1 (DIF_2_N) are configured > as TXD0 and TXD1 data lines as well. > This results in a bad Ethernet receive performance. Presumably this is > due to the eth_txd0 and eth_txd1 signal being routed to the wrong pins. > As a result of that data can only be transmitted on eth_txd2 and > eth_txd3. However, I have no scope to fully confirm this assumption. > > The vendor u-boot sources for Odroid-C1 use the following Ethernet > pinmux configuration: > SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, 0x3f4f); > SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_7, 0xf00000); > This translates to the following pin groups in the mainline kernel: > - register 6 bit 0: eth_rxd1 (DIF_0_P) > - register 6 bit 1: eth_rxd0 (DIF_0_N) > - register 6 bit 2: eth_rx_dv (DIF_1_P) > - register 6 bit 3: eth_rx_clk (DIF_1_N) > - register 6 bit 6: eth_tx_en (DIF_3_P) > - register 6 bit 8: eth_ref_clk (DIF_3_N) > - register 6 bit 9: eth_mdc (DIF_4_P) > - register 6 bit 10: eth_mdio_en (DIF_4_N) > - register 6 bit 11: eth_tx_clk (GPIOH_9) > - register 6 bit 12: eth_txd2 (GPIOH_8) > - register 6 bit 13: eth_txd3 (GPIOH_7) > - register 7 bit 20: eth_txd0_0 (GPIOH_6) > - register 7 bit 21: eth_txd1_0 (GPIOH_5) > - register 7 bit 22: eth_rxd3 (DIF_2_P) > - register 7 bit 23: eth_rxd2 (DIF_2_N) > > Drop the eth_txd0_1 and eth_txd1_1 groups from eth_rgmii_pins to fix the > Ethernet transmit performance on Odroid-C1. Also add the eth_rxd2 and > eth_rxd3 groups so we don't rely on the bootloader to set them up. > > iperf3 statistics before this change: > - transmitting from Odroid-C1: 741 Mbits/sec (0 retries) > - receiving on Odroid-C1: 199 Mbits/sec (1713 retries) > > iperf3 statistics after this change: > - transmitting from Odroid-C1: 667 Mbits/sec (0 retries) > - receiving on Odroid-C1: 750 Mbits/sec (0 retries) > > Fixes: b96446541d8390 ("ARM: dts: meson8b: extend ethernet controller description") > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > Cc: Emiliano Ingrassia <ingrassia@epigenesys.com> > Cc: Linus Lüssing <linus.luessing@c0d3.blue> Queued for v5.1 (branch: v5.1/dt) Kevin
On Thu, Jan 10, 2019 at 05:09:47PM -0800, Kevin Hilman wrote: > Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes: > > > According to the Odroid-C1+ schematics the Ethernet TXD1 signal is > > routed to GPIOH_5 and the TXD0 signal is routed to GPIOH_6. > > The public S805 datasheet shows that TXD0 can be routed to DIF_2_P and > > TXD1 can be routed to DIF_2_N instead. > > > > The pin groups eth_txd0_0 (GPIOH_6) and eth_txd0_1 (DIF_2_P) are both > > configured as Ethernet TXD0 and TXD1 data lines in meson8b.dtsi. At the > > same time eth_txd1_0 (GPIOH_5) and eth_txd1_1 (DIF_2_N) are configured > > as TXD0 and TXD1 data lines as well. > > This results in a bad Ethernet receive performance. Presumably this is > > due to the eth_txd0 and eth_txd1 signal being routed to the wrong pins. > > As a result of that data can only be transmitted on eth_txd2 and > > eth_txd3. However, I have no scope to fully confirm this assumption. > > > > The vendor u-boot sources for Odroid-C1 use the following Ethernet > > pinmux configuration: > > SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, 0x3f4f); > > SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_7, 0xf00000); > > This translates to the following pin groups in the mainline kernel: > > - register 6 bit 0: eth_rxd1 (DIF_0_P) > > - register 6 bit 1: eth_rxd0 (DIF_0_N) > > - register 6 bit 2: eth_rx_dv (DIF_1_P) > > - register 6 bit 3: eth_rx_clk (DIF_1_N) > > - register 6 bit 6: eth_tx_en (DIF_3_P) > > - register 6 bit 8: eth_ref_clk (DIF_3_N) > > - register 6 bit 9: eth_mdc (DIF_4_P) > > - register 6 bit 10: eth_mdio_en (DIF_4_N) > > - register 6 bit 11: eth_tx_clk (GPIOH_9) > > - register 6 bit 12: eth_txd2 (GPIOH_8) > > - register 6 bit 13: eth_txd3 (GPIOH_7) > > - register 7 bit 20: eth_txd0_0 (GPIOH_6) > > - register 7 bit 21: eth_txd1_0 (GPIOH_5) > > - register 7 bit 22: eth_rxd3 (DIF_2_P) > > - register 7 bit 23: eth_rxd2 (DIF_2_N) > > > > Drop the eth_txd0_1 and eth_txd1_1 groups from eth_rgmii_pins to fix the > > Ethernet transmit performance on Odroid-C1. Also add the eth_rxd2 and > > eth_rxd3 groups so we don't rely on the bootloader to set them up. > > > > iperf3 statistics before this change: > > - transmitting from Odroid-C1: 741 Mbits/sec (0 retries) > > - receiving on Odroid-C1: 199 Mbits/sec (1713 retries) > > > > iperf3 statistics after this change: > > - transmitting from Odroid-C1: 667 Mbits/sec (0 retries) > > - receiving on Odroid-C1: 750 Mbits/sec (0 retries) > > > > Fixes: b96446541d8390 ("ARM: dts: meson8b: extend ethernet controller description") > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > > Cc: Emiliano Ingrassia <ingrassia@epigenesys.com> > > Cc: Linus Lüssing <linus.luessing@c0d3.blue> > > Queued for v5.1 (branch: v5.1/dt) > > Kevin Tested-by: Emiliano Ingrassia <ingrassia@epigenesys.com> Reviewed-by: Emiliano Ingrassia <ingrassia@epigenesys.com> Emiliano
Hi Kevin, On Fri, Jan 11, 2019 at 2:09 AM Kevin Hilman <khilman@baylibre.com> wrote: > > Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes: > > > According to the Odroid-C1+ schematics the Ethernet TXD1 signal is > > routed to GPIOH_5 and the TXD0 signal is routed to GPIOH_6. > > The public S805 datasheet shows that TXD0 can be routed to DIF_2_P and > > TXD1 can be routed to DIF_2_N instead. > > > > The pin groups eth_txd0_0 (GPIOH_6) and eth_txd0_1 (DIF_2_P) are both > > configured as Ethernet TXD0 and TXD1 data lines in meson8b.dtsi. At the > > same time eth_txd1_0 (GPIOH_5) and eth_txd1_1 (DIF_2_N) are configured > > as TXD0 and TXD1 data lines as well. > > This results in a bad Ethernet receive performance. Presumably this is > > due to the eth_txd0 and eth_txd1 signal being routed to the wrong pins. > > As a result of that data can only be transmitted on eth_txd2 and > > eth_txd3. However, I have no scope to fully confirm this assumption. > > > > The vendor u-boot sources for Odroid-C1 use the following Ethernet > > pinmux configuration: > > SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, 0x3f4f); > > SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_7, 0xf00000); > > This translates to the following pin groups in the mainline kernel: > > - register 6 bit 0: eth_rxd1 (DIF_0_P) > > - register 6 bit 1: eth_rxd0 (DIF_0_N) > > - register 6 bit 2: eth_rx_dv (DIF_1_P) > > - register 6 bit 3: eth_rx_clk (DIF_1_N) > > - register 6 bit 6: eth_tx_en (DIF_3_P) > > - register 6 bit 8: eth_ref_clk (DIF_3_N) > > - register 6 bit 9: eth_mdc (DIF_4_P) > > - register 6 bit 10: eth_mdio_en (DIF_4_N) > > - register 6 bit 11: eth_tx_clk (GPIOH_9) > > - register 6 bit 12: eth_txd2 (GPIOH_8) > > - register 6 bit 13: eth_txd3 (GPIOH_7) > > - register 7 bit 20: eth_txd0_0 (GPIOH_6) > > - register 7 bit 21: eth_txd1_0 (GPIOH_5) > > - register 7 bit 22: eth_rxd3 (DIF_2_P) > > - register 7 bit 23: eth_rxd2 (DIF_2_N) > > > > Drop the eth_txd0_1 and eth_txd1_1 groups from eth_rgmii_pins to fix the > > Ethernet transmit performance on Odroid-C1. Also add the eth_rxd2 and > > eth_rxd3 groups so we don't rely on the bootloader to set them up. > > > > iperf3 statistics before this change: > > - transmitting from Odroid-C1: 741 Mbits/sec (0 retries) > > - receiving on Odroid-C1: 199 Mbits/sec (1713 retries) > > > > iperf3 statistics after this change: > > - transmitting from Odroid-C1: 667 Mbits/sec (0 retries) > > - receiving on Odroid-C1: 750 Mbits/sec (0 retries) > > > > Fixes: b96446541d8390 ("ARM: dts: meson8b: extend ethernet controller description") > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > > Cc: Emiliano Ingrassia <ingrassia@epigenesys.com> > > Cc: Linus Lüssing <linus.luessing@c0d3.blue> > > Queued for v5.1 (branch: v5.1/dt) do you know what happened to this patch? I can't find it in v5.1/dt let me know if I should re-send it Regards Martin
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes: > Hi Kevin, > > On Fri, Jan 11, 2019 at 2:09 AM Kevin Hilman <khilman@baylibre.com> wrote: >> >> Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes: >> >> > According to the Odroid-C1+ schematics the Ethernet TXD1 signal is >> > routed to GPIOH_5 and the TXD0 signal is routed to GPIOH_6. >> > The public S805 datasheet shows that TXD0 can be routed to DIF_2_P and >> > TXD1 can be routed to DIF_2_N instead. >> > >> > The pin groups eth_txd0_0 (GPIOH_6) and eth_txd0_1 (DIF_2_P) are both >> > configured as Ethernet TXD0 and TXD1 data lines in meson8b.dtsi. At the >> > same time eth_txd1_0 (GPIOH_5) and eth_txd1_1 (DIF_2_N) are configured >> > as TXD0 and TXD1 data lines as well. >> > This results in a bad Ethernet receive performance. Presumably this is >> > due to the eth_txd0 and eth_txd1 signal being routed to the wrong pins. >> > As a result of that data can only be transmitted on eth_txd2 and >> > eth_txd3. However, I have no scope to fully confirm this assumption. >> > >> > The vendor u-boot sources for Odroid-C1 use the following Ethernet >> > pinmux configuration: >> > SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, 0x3f4f); >> > SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_7, 0xf00000); >> > This translates to the following pin groups in the mainline kernel: >> > - register 6 bit 0: eth_rxd1 (DIF_0_P) >> > - register 6 bit 1: eth_rxd0 (DIF_0_N) >> > - register 6 bit 2: eth_rx_dv (DIF_1_P) >> > - register 6 bit 3: eth_rx_clk (DIF_1_N) >> > - register 6 bit 6: eth_tx_en (DIF_3_P) >> > - register 6 bit 8: eth_ref_clk (DIF_3_N) >> > - register 6 bit 9: eth_mdc (DIF_4_P) >> > - register 6 bit 10: eth_mdio_en (DIF_4_N) >> > - register 6 bit 11: eth_tx_clk (GPIOH_9) >> > - register 6 bit 12: eth_txd2 (GPIOH_8) >> > - register 6 bit 13: eth_txd3 (GPIOH_7) >> > - register 7 bit 20: eth_txd0_0 (GPIOH_6) >> > - register 7 bit 21: eth_txd1_0 (GPIOH_5) >> > - register 7 bit 22: eth_rxd3 (DIF_2_P) >> > - register 7 bit 23: eth_rxd2 (DIF_2_N) >> > >> > Drop the eth_txd0_1 and eth_txd1_1 groups from eth_rgmii_pins to fix the >> > Ethernet transmit performance on Odroid-C1. Also add the eth_rxd2 and >> > eth_rxd3 groups so we don't rely on the bootloader to set them up. >> > >> > iperf3 statistics before this change: >> > - transmitting from Odroid-C1: 741 Mbits/sec (0 retries) >> > - receiving on Odroid-C1: 199 Mbits/sec (1713 retries) >> > >> > iperf3 statistics after this change: >> > - transmitting from Odroid-C1: 667 Mbits/sec (0 retries) >> > - receiving on Odroid-C1: 750 Mbits/sec (0 retries) >> > >> > Fixes: b96446541d8390 ("ARM: dts: meson8b: extend ethernet controller description") >> > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> >> > Cc: Emiliano Ingrassia <ingrassia@epigenesys.com> >> > Cc: Linus Lüssing <linus.luessing@c0d3.blue> >> >> Queued for v5.1 (branch: v5.1/dt) > do you know what happened to this patch? I can't find it in v5.1/dt Hmm, I'm not sure what happened to it, but I (re)added it to v5.1/dt just now. Kevin
On Thu, Feb 7, 2019 at 4:05 AM Kevin Hilman <khilman@baylibre.com> wrote: [...] > >> Queued for v5.1 (branch: v5.1/dt) > > do you know what happened to this patch? I can't find it in v5.1/dt > > Hmm, I'm not sure what happened to it, but I (re)added it to v5.1/dt > just now. perfect - thank you!
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 22d775460767..dc125769fe85 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -270,9 +270,7 @@ groups = "eth_tx_clk", "eth_tx_en", "eth_txd1_0", - "eth_txd1_1", "eth_txd0_0", - "eth_txd0_1", "eth_rx_clk", "eth_rx_dv", "eth_rxd1", @@ -281,7 +279,9 @@ "eth_mdc", "eth_ref_clk", "eth_txd2", - "eth_txd3"; + "eth_txd3", + "eth_rxd3", + "eth_rxd2"; function = "ethernet"; bias-disable; };
According to the Odroid-C1+ schematics the Ethernet TXD1 signal is routed to GPIOH_5 and the TXD0 signal is routed to GPIOH_6. The public S805 datasheet shows that TXD0 can be routed to DIF_2_P and TXD1 can be routed to DIF_2_N instead. The pin groups eth_txd0_0 (GPIOH_6) and eth_txd0_1 (DIF_2_P) are both configured as Ethernet TXD0 and TXD1 data lines in meson8b.dtsi. At the same time eth_txd1_0 (GPIOH_5) and eth_txd1_1 (DIF_2_N) are configured as TXD0 and TXD1 data lines as well. This results in a bad Ethernet receive performance. Presumably this is due to the eth_txd0 and eth_txd1 signal being routed to the wrong pins. As a result of that data can only be transmitted on eth_txd2 and eth_txd3. However, I have no scope to fully confirm this assumption. The vendor u-boot sources for Odroid-C1 use the following Ethernet pinmux configuration: SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, 0x3f4f); SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_7, 0xf00000); This translates to the following pin groups in the mainline kernel: - register 6 bit 0: eth_rxd1 (DIF_0_P) - register 6 bit 1: eth_rxd0 (DIF_0_N) - register 6 bit 2: eth_rx_dv (DIF_1_P) - register 6 bit 3: eth_rx_clk (DIF_1_N) - register 6 bit 6: eth_tx_en (DIF_3_P) - register 6 bit 8: eth_ref_clk (DIF_3_N) - register 6 bit 9: eth_mdc (DIF_4_P) - register 6 bit 10: eth_mdio_en (DIF_4_N) - register 6 bit 11: eth_tx_clk (GPIOH_9) - register 6 bit 12: eth_txd2 (GPIOH_8) - register 6 bit 13: eth_txd3 (GPIOH_7) - register 7 bit 20: eth_txd0_0 (GPIOH_6) - register 7 bit 21: eth_txd1_0 (GPIOH_5) - register 7 bit 22: eth_rxd3 (DIF_2_P) - register 7 bit 23: eth_rxd2 (DIF_2_N) Drop the eth_txd0_1 and eth_txd1_1 groups from eth_rgmii_pins to fix the Ethernet transmit performance on Odroid-C1. Also add the eth_rxd2 and eth_rxd3 groups so we don't rely on the bootloader to set them up. iperf3 statistics before this change: - transmitting from Odroid-C1: 741 Mbits/sec (0 retries) - receiving on Odroid-C1: 199 Mbits/sec (1713 retries) iperf3 statistics after this change: - transmitting from Odroid-C1: 667 Mbits/sec (0 retries) - receiving on Odroid-C1: 750 Mbits/sec (0 retries) Fixes: b96446541d8390 ("ARM: dts: meson8b: extend ethernet controller description") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: Emiliano Ingrassia <ingrassia@epigenesys.com> Cc: Linus Lüssing <linus.luessing@c0d3.blue> --- arch/arm/boot/dts/meson8b.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)