diff mbox series

[resend,v1,1/2] dt-bindings: clock: add clock for MT2712

Message ID 20181214020417.2871-3-weiyi.lu@mediatek.com (mailing list archive)
State New, archived
Headers show
Series update Mediatek MT2712 clock | expand

Commit Message

Weiyi Lu Dec. 14, 2018, 2:04 a.m. UTC 
Add new clock according to 3rd ECO design change.
It's the parent clock of audio clock mux.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
 include/dt-bindings/clock/mt2712-clk.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Rob Herring (Arm) Dec. 20, 2018, 8:43 p.m. UTC | #1 
On Fri, 14 Dec 2018 10:04:16 +0800, Weiyi Lu wrote:
> Add new clock according to 3rd ECO design change.
> It's the parent clock of audio clock mux.
> 
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
>  include/dt-bindings/clock/mt2712-clk.h | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>
Stephen Boyd Feb. 5, 2019, 9:29 p.m. UTC | #2 
Quoting Weiyi Lu (2018-12-13 18:04:16)
> Add new clock according to 3rd ECO design change.
> It's the parent clock of audio clock mux.
> 
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---

Applied to clk-next
diff mbox series

Patch

diff --git a/include/dt-bindings/clock/mt2712-clk.h b/include/dt-bindings/clock/mt2712-clk.h
index 76265836a1e1..c3b29dff9c0e 100644
--- a/include/dt-bindings/clock/mt2712-clk.h
+++ b/include/dt-bindings/clock/mt2712-clk.h
@@ -228,7 +228,8 @@ 
 #define CLK_TOP_NFI2X_EN		189
 #define CLK_TOP_NFIECC_EN		190
 #define CLK_TOP_NFI1X_CK_EN		191
-#define CLK_TOP_NR_CLK			192
+#define CLK_TOP_APLL2_D3		192
+#define CLK_TOP_NR_CLK			193
 
 /* INFRACFG */