| Message ID | 20190205185902.106085-7-evgreen@chromium.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | phy: qcom-ufs: Enable regulators to be off in suspend | expand |
On 06/02/19 12:29 AM, Evan Green wrote: > Expose a reset controller that the phy will later use to control its > own PHY reset in the UFS controller. This will enable the combining > of PHY init functionality into a single function. > > Signed-off-by: Evan Green <evgreen@chromium.org> I'd like to get ACK from scsi/ufs/ MAINTAINER Vinayak for me merge it in PHY tree. Thanks Kishon > > --- > Note: The remaining changes in this series need this change, since > the PHYs now depend on getting the reset controller. > > Changes in v3: > - Refactor to only expose the reset controller in one change (Stephen). > - Add period to comment (Stephen). > - Reset err to 0 in ignored error case (Stephen). > - Add include of reset-controller.h (Stephen) > > Changes in v2: > - Remove include of reset.h (Stephen) > - Fix error print of phy_power_on (Stephen) > - Comment for reset controller warnings on id != 0 (Stephen) > - Add static to ufs_qcom_reset_ops (Stephen). > > drivers/scsi/ufs/Kconfig | 1 + > drivers/scsi/ufs/ufs-qcom.c | 52 +++++++++++++++++++++++++++++++++++++ > drivers/scsi/ufs/ufs-qcom.h | 4 +++ > 3 files changed, 57 insertions(+) > > diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig > index 2ddbb26d9c26..63c5c4115981 100644 > --- a/drivers/scsi/ufs/Kconfig > +++ b/drivers/scsi/ufs/Kconfig > @@ -100,6 +100,7 @@ config SCSI_UFS_QCOM > tristate "QCOM specific hooks to UFS controller platform driver" > depends on SCSI_UFSHCD_PLATFORM && ARCH_QCOM > select PHY_QCOM_UFS > + select RESET_CONTROLLER > help > This selects the QCOM specific additions to UFSHCD platform driver. > UFS host on QCOM needs some vendor specific configuration before > diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c > index 3aeadb14aae1..ab05ef5cfdcd 100644 > --- a/drivers/scsi/ufs/ufs-qcom.c > +++ b/drivers/scsi/ufs/ufs-qcom.c > @@ -16,6 +16,7 @@ > #include <linux/of.h> > #include <linux/platform_device.h> > #include <linux/phy/phy.h> > +#include <linux/reset-controller.h> > > #include "ufshcd.h" > #include "ufshcd-pltfrm.h" > @@ -49,6 +50,11 @@ static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); > static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, > u32 clk_cycles); > > +static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) > +{ > + return container_of(rcd, struct ufs_qcom_host, rcdev); > +} > + > static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len, > const char *prefix, void *priv) > { > @@ -1147,6 +1153,41 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, > return err; > } > > +static int > +ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) > +{ > + struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); > + > + /* Currently this code only knows about a single reset. */ > + WARN_ON(id); > + ufs_qcom_assert_reset(host->hba); > + /* provide 1ms delay to let the reset pulse propagate. */ > + usleep_range(1000, 1100); > + return 0; > +} > + > +static int > +ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) > +{ > + struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); > + > + /* Currently this code only knows about a single reset. */ > + WARN_ON(id); > + ufs_qcom_deassert_reset(host->hba); > + > + /* > + * after reset deassertion, phy will need all ref clocks, > + * voltage, current to settle down before starting serdes. > + */ > + usleep_range(1000, 1100); > + return 0; > +} > + > +static const struct reset_control_ops ufs_qcom_reset_ops = { > + .assert = ufs_qcom_reset_assert, > + .deassert = ufs_qcom_reset_deassert, > +}; > + > #define ANDROID_BOOT_DEV_MAX 30 > static char android_boot_dev[ANDROID_BOOT_DEV_MAX]; > > @@ -1191,6 +1232,17 @@ static int ufs_qcom_init(struct ufs_hba *hba) > host->hba = hba; > ufshcd_set_variant(hba, host); > > + /* Fire up the reset controller. Failure here is non-fatal. */ > + host->rcdev.of_node = dev->of_node; > + host->rcdev.ops = &ufs_qcom_reset_ops; > + host->rcdev.owner = dev->driver->owner; > + host->rcdev.nr_resets = 1; > + err = devm_reset_controller_register(dev, &host->rcdev); > + if (err) { > + dev_warn(dev, "Failed to register reset controller\n"); > + err = 0; > + } > + > /* > * voting/devoting device ref_clk source is time consuming hence > * skip devoting it during aggressive clock gating. This clock > diff --git a/drivers/scsi/ufs/ufs-qcom.h b/drivers/scsi/ufs/ufs-qcom.h > index c114826316eb..68a880185752 100644 > --- a/drivers/scsi/ufs/ufs-qcom.h > +++ b/drivers/scsi/ufs/ufs-qcom.h > @@ -14,6 +14,8 @@ > #ifndef UFS_QCOM_H_ > #define UFS_QCOM_H_ > > +#include <linux/reset-controller.h> > + > #define MAX_UFS_QCOM_HOSTS 1 > #define MAX_U32 (~(u32)0) > #define MPHY_TX_FSM_STATE 0x41 > @@ -237,6 +239,8 @@ struct ufs_qcom_host { > /* Bitmask for enabling debug prints */ > u32 dbg_print_en; > struct ufs_qcom_testbus testbus; > + > + struct reset_controller_dev rcdev; > }; > > static inline u32 >
On 06/02/2019 12:42, Kishon Vijay Abraham I wrote: > On 06/02/19 12:29 AM, Evan Green wrote: > >> Expose a reset controller that the phy will later use to control its >> own PHY reset in the UFS controller. This will enable the combining >> of PHY init functionality into a single function. >> >> Signed-off-by: Evan Green <evgreen@chromium.org> > > I'd like to get ACK from scsi/ufs/ MAINTAINER Vinayak for me merge it in PHY tree. Kishon, I haven't seen any messages from Vinayak in a while. https://patchwork.kernel.org/patch/10795501/ New reviewers are Alim, Avri, and Pedro (haven't heard from Pedro yet). Regards.
Hi Marc, On 06/02/19 5:24 PM, Marc Gonzalez wrote: > On 06/02/2019 12:42, Kishon Vijay Abraham I wrote: > >> On 06/02/19 12:29 AM, Evan Green wrote: >> >>> Expose a reset controller that the phy will later use to control its >>> own PHY reset in the UFS controller. This will enable the combining >>> of PHY init functionality into a single function. >>> >>> Signed-off-by: Evan Green <evgreen@chromium.org> >> >> I'd like to get ACK from scsi/ufs/ MAINTAINER Vinayak for me merge it in PHY tree. > > Kishon, I haven't seen any messages from Vinayak in a while. > > https://patchwork.kernel.org/patch/10795501/ > > New reviewers are Alim, Avri, and Pedro (haven't heard from Pedro yet). Thanks for letting me know. Alim, Avri, Can you give your ACK for this patch? Thanks Kishon > > Regards. >
Hi, > On 06/02/19 12:29 AM, Evan Green wrote: > > Expose a reset controller that the phy will later use to control its > > own PHY reset in the UFS controller. This will enable the combining > > of PHY init functionality into a single function. > > > > Signed-off-by: Evan Green <evgreen@chromium.org> > > I'd like to get ACK from scsi/ufs/ MAINTAINER Vinayak for me merge it in PHY > tree. Looks like this series is qcom specific, and has less impact of the ufs core driver. > > + err = devm_reset_controller_register(dev, &host->rcdev); Just my 2 cents: Isn't this should be done somewhere in drivers/clk/qcom, Like its done for any other qcom board?
Quoting Avri Altman (2019-02-06 05:57:17) > Hi, > > > On 06/02/19 12:29 AM, Evan Green wrote: > > > Expose a reset controller that the phy will later use to control its > > > own PHY reset in the UFS controller. This will enable the combining > > > of PHY init functionality into a single function. > > > > > > Signed-off-by: Evan Green <evgreen@chromium.org> > > > > I'd like to get ACK from scsi/ufs/ MAINTAINER Vinayak for me merge it in PHY > > tree. > Looks like this series is qcom specific, and has less impact of the ufs core driver. > > > > + err = devm_reset_controller_register(dev, &host->rcdev); > Just my 2 cents: > Isn't this should be done somewhere in drivers/clk/qcom, > Like its done for any other qcom board? It's not a clk controller, so I don't see how that makes sense. There are clk/reset controllers on qcom platforms, and so we've combined them into the same overall driver there because those resets affect clk operations and vice-versa. But this looks like some sort of reset in the phy or the controller itself and isn't the "clk type" resets that we implement in drivers/clk/qcom/
Quoting Evan Green (2019-02-05 10:59:00) > Expose a reset controller that the phy will later use to control its > own PHY reset in the UFS controller. This will enable the combining > of PHY init functionality into a single function. > > Signed-off-by: Evan Green <evgreen@chromium.org> > > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig index 2ddbb26d9c26..63c5c4115981 100644 --- a/drivers/scsi/ufs/Kconfig +++ b/drivers/scsi/ufs/Kconfig @@ -100,6 +100,7 @@ config SCSI_UFS_QCOM tristate "QCOM specific hooks to UFS controller platform driver" depends on SCSI_UFSHCD_PLATFORM && ARCH_QCOM select PHY_QCOM_UFS + select RESET_CONTROLLER help This selects the QCOM specific additions to UFSHCD platform driver. UFS host on QCOM needs some vendor specific configuration before diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c index 3aeadb14aae1..ab05ef5cfdcd 100644 --- a/drivers/scsi/ufs/ufs-qcom.c +++ b/drivers/scsi/ufs/ufs-qcom.c @@ -16,6 +16,7 @@ #include <linux/of.h> #include <linux/platform_device.h> #include <linux/phy/phy.h> +#include <linux/reset-controller.h> #include "ufshcd.h" #include "ufshcd-pltfrm.h" @@ -49,6 +50,11 @@ static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, u32 clk_cycles); +static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) +{ + return container_of(rcd, struct ufs_qcom_host, rcdev); +} + static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len, const char *prefix, void *priv) { @@ -1147,6 +1153,41 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, return err; } +static int +ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); + + /* Currently this code only knows about a single reset. */ + WARN_ON(id); + ufs_qcom_assert_reset(host->hba); + /* provide 1ms delay to let the reset pulse propagate. */ + usleep_range(1000, 1100); + return 0; +} + +static int +ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); + + /* Currently this code only knows about a single reset. */ + WARN_ON(id); + ufs_qcom_deassert_reset(host->hba); + + /* + * after reset deassertion, phy will need all ref clocks, + * voltage, current to settle down before starting serdes. + */ + usleep_range(1000, 1100); + return 0; +} + +static const struct reset_control_ops ufs_qcom_reset_ops = { + .assert = ufs_qcom_reset_assert, + .deassert = ufs_qcom_reset_deassert, +}; + #define ANDROID_BOOT_DEV_MAX 30 static char android_boot_dev[ANDROID_BOOT_DEV_MAX]; @@ -1191,6 +1232,17 @@ static int ufs_qcom_init(struct ufs_hba *hba) host->hba = hba; ufshcd_set_variant(hba, host); + /* Fire up the reset controller. Failure here is non-fatal. */ + host->rcdev.of_node = dev->of_node; + host->rcdev.ops = &ufs_qcom_reset_ops; + host->rcdev.owner = dev->driver->owner; + host->rcdev.nr_resets = 1; + err = devm_reset_controller_register(dev, &host->rcdev); + if (err) { + dev_warn(dev, "Failed to register reset controller\n"); + err = 0; + } + /* * voting/devoting device ref_clk source is time consuming hence * skip devoting it during aggressive clock gating. This clock diff --git a/drivers/scsi/ufs/ufs-qcom.h b/drivers/scsi/ufs/ufs-qcom.h index c114826316eb..68a880185752 100644 --- a/drivers/scsi/ufs/ufs-qcom.h +++ b/drivers/scsi/ufs/ufs-qcom.h @@ -14,6 +14,8 @@ #ifndef UFS_QCOM_H_ #define UFS_QCOM_H_ +#include <linux/reset-controller.h> + #define MAX_UFS_QCOM_HOSTS 1 #define MAX_U32 (~(u32)0) #define MPHY_TX_FSM_STATE 0x41 @@ -237,6 +239,8 @@ struct ufs_qcom_host { /* Bitmask for enabling debug prints */ u32 dbg_print_en; struct ufs_qcom_testbus testbus; + + struct reset_controller_dev rcdev; }; static inline u32
Expose a reset controller that the phy will later use to control its own PHY reset in the UFS controller. This will enable the combining of PHY init functionality into a single function. Signed-off-by: Evan Green <evgreen@chromium.org> --- Note: The remaining changes in this series need this change, since the PHYs now depend on getting the reset controller. Changes in v3: - Refactor to only expose the reset controller in one change (Stephen). - Add period to comment (Stephen). - Reset err to 0 in ignored error case (Stephen). - Add include of reset-controller.h (Stephen) Changes in v2: - Remove include of reset.h (Stephen) - Fix error print of phy_power_on (Stephen) - Comment for reset controller warnings on id != 0 (Stephen) - Add static to ufs_qcom_reset_ops (Stephen). drivers/scsi/ufs/Kconfig | 1 + drivers/scsi/ufs/ufs-qcom.c | 52 +++++++++++++++++++++++++++++++++++++ drivers/scsi/ufs/ufs-qcom.h | 4 +++ 3 files changed, 57 insertions(+)