| Message ID | 1544758829-10327-1-git-send-email-honghui.zhang@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | [RFC] PCI/portdrv: Support for subtractive decode bridge | expand |
Hi Honghui, On Fri, Dec 14, 2018 at 11:40:29AM +0800, honghui.zhang@mediatek.com wrote: > From: Honghui Zhang <honghui.zhang@mediatek.com> > > The Class Code for subtractive decode PCI-to-PCI bridge is 060401h, > change the class_mask values to make portdrv support this type bridge. I assume you have a Root Port or Switch Port that supports subtractive decode? I'm trying to understand how such a device would work. Out of curiosity, can you show the "lspci -vv" output for the device and the downstream devices of interest? Do you happen to know whether this functionality is configurable, e.g., is there some way software can enable or disable subtractive decode? I assume this would be some device-specific thing, because I can't find anything in the Bridge Control register or similar. The PCIe spec doesn't even contain the word "subtractive". The "PCI Express to PCI/PCI-X Bridge Specification", r1.0, says a PCI Express bridge (which would include Root Ports and Switch Ports) has a Class Code of 0x060400 (Non-Subtractive PCI-PCI Bridge) (sec 1.1). Sec 1.3.4 says subtractive decode on the primary interface is "not applicable or outside the scope of this spec". Bjorn > Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> > --- > drivers/pci/pcie/portdrv_pci.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c > index eef22dc..86926ea 100644 > --- a/drivers/pci/pcie/portdrv_pci.c > +++ b/drivers/pci/pcie/portdrv_pci.c > @@ -179,7 +179,7 @@ static void pcie_portdrv_err_resume(struct pci_dev *dev) > */ > static const struct pci_device_id port_pci_ids[] = { { > /* handle any PCI-Express port */ > - PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0), > + PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0x01), > }, { /* end: all zeroes */ } > }; > > -- > 2.6.4 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Thu, Feb 07, 2019 at 09:18:16AM -0600, Bjorn Helgaas wrote: > On Fri, Dec 14, 2018 at 11:40:29AM +0800, honghui.zhang@mediatek.com wrote: > > From: Honghui Zhang <honghui.zhang@mediatek.com> > > > > The Class Code for subtractive decode PCI-to-PCI bridge is 060401h, > > change the class_mask values to make portdrv support this type bridge. > > I assume you have a Root Port or Switch Port that supports subtractive > decode? I'm trying to understand how such a device would work. > > Out of curiosity, can you show the "lspci -vv" output for the device > and the downstream devices of interest? Actually, since subtractive decode has to do with how the bridge interacts with its *peers*, what would be interesting is the host bridge window information from ACPI _CRS or DT and the lspci info for everything under that host bridge. Assuming we're talking about a Root Port, I guess that would mean anything inside the host bridge windows but outside the positive decode windows (the normal PCI-PCI bridge apertures in the Root Ports) would be claimed by the subtractive decode Root Port? I guess you would want this because this path ultimately leads to an ISA or similar bus where you don't know what resources the device actually consumes? Bjorn
On Thu, 2019-02-07 at 09:18 -0600, Bjorn Helgaas wrote: > Hi Honghui, > > On Fri, Dec 14, 2018 at 11:40:29AM +0800, honghui.zhang@mediatek.com wrote: > > From: Honghui Zhang <honghui.zhang@mediatek.com> > > > > The Class Code for subtractive decode PCI-to-PCI bridge is 060401h, > > change the class_mask values to make portdrv support this type bridge. > > I assume you have a Root Port or Switch Port that supports subtractive > decode? I'm trying to understand how such a device would work. > Hi, Bjorn, Yes, most of Mediatek's RC device have set the class type as 060401h as HW default values, include mt2712 and mt7622. Those RC device work fine with all I have tried EP device except that the portdrv was not attached to those device. But no scenario need those service as far as I know. > Out of curiosity, can you show the "lspci -vv" output for the device > and the downstream devices of interest? > lspci only read the class type 0604h, it does not care about the subordinate values of the class type. I will put the "lspci -vv" output at bottom of this mail. > Do you happen to know whether this functionality is configurable, > e.g., is there some way software can enable or disable subtractive > decode? I assume this would be some device-specific thing, because I > can't find anything in the Bridge Control register or similar. The > PCIe spec doesn't even contain the word "subtractive". > Those class type values for Mediatek's RC has a register which could be used to change its values. We never touch this backdoor register since without the portdrv attached is fine, nobody ask for the port service yet. I did some homework for the subtractive decode PCI-to-PCI bridge, and did not found much more information about that. I guess those port service should also support subtractive bridge since spec does not forbidden that. > The "PCI Express to PCI/PCI-X Bridge Specification", r1.0, says a PCI > Express bridge (which would include Root Ports and Switch Ports) has a > Class Code of 0x060400 (Non-Subtractive PCI-PCI Bridge) (sec 1.1). > > Sec 1.3.4 says subtractive decode on the primary interface is "not > applicable or outside the scope of this spec". > > Bjorn > # lspci -vvv 00:01.0 Class 0604: Device 14c3:5396 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 264 Region 0: Memory at <unassigned> (64-bit, prefetchable) Bus: primary=00, secondary=01, subordinate=01, sec-latency=64 I/O behind bridge: 00000000-00000fff Memory behind bridge: 20000000-206fffff Prefetchable memory behind bridge: 00000000-000fffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 000000000807a0c0 Data: 0000 Capabilities: [78] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [80] Express (v2) Root Port (Slot+), MSI 01 DevCap: MaxPayload 256 bytes, PhantFunc 0 ExtTag- RBE+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend+ LnkCap: Port #1, Speed 5GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <64ns, L1 <2us ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 128 bytes Disabled- CommClk + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #0, PowerLimit 0.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Not Supported ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [100 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Capabilities: [400 v1] L1 PM Substates L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1 + L1_PM_Substates+ PortCommonModeRestoreTime=30us PortTPowerOnTime=10us Capabilities: [600 v1] Latency Tolerance Reporting Max snoop latency: 0ns Max no snoop latency: 0ns Kernel driver in use: pcieport 01:00.0 Class 0200: Device 8086:1521 (rev 01) Subsystem: Device 1d1a:0000 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 128 bytes Interrupt: pin A routed to IRQ 260 Region 0: Memory at 20000000 (32-bit, non-prefetchable) [size=1M] Region 3: Memory at 20600000 (32-bit, non-prefetchable) [size=16K] [virtual] Expansion ROM at 20400000 [disabled] [size=512K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0 +,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+ Address: 0000000000000000 Data: 0000 Masking: 00000000 Pending: 00000000 Capabilities: [70] MSI-X: Enable+ Count=10 Masked- Vector table: BAR=3 offset=00000000 PBA: BAR=3 offset=00002000 Capabilities: [a0] Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #1, Speed 5GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <32us ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR+, OBFF Not Supported DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [100 v2] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [140 v1] Device Serial Number 2c-53-4a-ff-ff-03-46-80 Capabilities: [150 v1] Alternative Routing-ID Interpretation (ARI) ARICap: MFVC- ACS-, Next Function: 1 ARICtl: MFVC- ACS-, Function Group: 0 Capabilities: [160 v1] Single Root I/O Virtualization (SR-IOV) IOVCap: Migration-, Interrupt Message Number: 000 IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy- IOVSta: Migration- Initial VFs: 8, Total VFs: 8, Number of VFs: 0, Function Dependency Link: 00 VF offset: 384, stride: 4, Device ID: 1520 Supported Page Size: 00000553, System Page Size: 00000001 VF Migration: offset: 00000000, BIR: 0 Capabilities: [1a0 v1] Transaction Processing Hints Device specific mode supported Steering table in TPH capability structure Capabilities: [1c0 v1] Latency Tolerance Reporting Max snoop latency: 0ns Max no snoop latency: 0ns Capabilities: [1d0 v1] Access Control Services ACSCap: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- Kernel driver in use: igb 01:00.1 Class 0200: Device 8086:1521 (rev 01) Subsystem: Device 1d1a:0000 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 128 bytes Interrupt: pin B routed to IRQ 261 Region 0: Memory at 20100000 (32-bit, non-prefetchable) [size=1M] Region 3: Memory at 20604000 (32-bit, non-prefetchable) [size=16K] [virtual] Expansion ROM at 20480000 [disabled] [size=512K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0 +,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+ Address: 0000000000000000 Data: 0000 Masking: 00000000 Pending: 00000000 Capabilities: [70] MSI-X: Enable+ Count=10 Masked- Vector table: BAR=3 offset=00000000 PBA: BAR=3 offset=00002000 Capabilities: [a0] Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #1, Speed 5GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <32us ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR+, OBFF Not Supported DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [100 v2] Advanced Error Reporting ...... ...... > > Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> > > --- > > drivers/pci/pcie/portdrv_pci.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c > > index eef22dc..86926ea 100644 > > --- a/drivers/pci/pcie/portdrv_pci.c > > +++ b/drivers/pci/pcie/portdrv_pci.c > > @@ -179,7 +179,7 @@ static void pcie_portdrv_err_resume(struct pci_dev *dev) > > */ > > static const struct pci_device_id port_pci_ids[] = { { > > /* handle any PCI-Express port */ > > - PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0), > > + PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0x01), > > }, { /* end: all zeroes */ } > > }; > > > > -- > > 2.6.4 > > > > > > _______________________________________________ > > linux-arm-kernel mailing list > > linux-arm-kernel@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Thu, 2019-02-07 at 13:52 -0600, Bjorn Helgaas wrote: > On Thu, Feb 07, 2019 at 09:18:16AM -0600, Bjorn Helgaas wrote: > > On Fri, Dec 14, 2018 at 11:40:29AM +0800, honghui.zhang@mediatek.com wrote: > > > From: Honghui Zhang <honghui.zhang@mediatek.com> > > > > > > The Class Code for subtractive decode PCI-to-PCI bridge is 060401h, > > > change the class_mask values to make portdrv support this type bridge. > > > > I assume you have a Root Port or Switch Port that supports subtractive > > decode? I'm trying to understand how such a device would work. > > > > Out of curiosity, can you show the "lspci -vv" output for the device > > and the downstream devices of interest? > > Actually, since subtractive decode has to do with how the bridge > interacts with its *peers*, what would be interesting is the host > bridge window information from ACPI _CRS or DT and the lspci info for > everything under that host bridge. > > Assuming we're talking about a Root Port, I guess that would mean > anything inside the host bridge windows but outside the positive > decode windows (the normal PCI-PCI bridge apertures in the Root Ports) > would be claimed by the subtractive decode Root Port? Per my understanding, mediatek's Root Port does not claim anything, or it's fine to assign no resource which is dedicated to this bridge. Those information could be got through lspci output which is attached in the last mail. All the resource it claimed is from the subordinate device, bridge itself does not need any special resource. > > I guess you would want this because this path ultimately leads to an > ISA or similar bus where you don't know what resources the device > actually consumes? > I was not get to that far, I just want to start a discussion about this, since spec does not forbidden subtractive bridge to support port service. Thanks. > Bjorn
On Tue, Feb 12, 2019 at 10:57:29AM +0800, Honghui Zhang wrote: > On Thu, 2019-02-07 at 09:18 -0600, Bjorn Helgaas wrote: > > On Fri, Dec 14, 2018 at 11:40:29AM +0800, honghui.zhang@mediatek.com wrote: > > > From: Honghui Zhang <honghui.zhang@mediatek.com> > > > > > > The Class Code for subtractive decode PCI-to-PCI bridge is 060401h, > > > change the class_mask values to make portdrv support this type bridge. > > > > I assume you have a Root Port or Switch Port that supports subtractive > > decode? I'm trying to understand how such a device would work. > > Yes, most of Mediatek's RC device have set the class type as 060401h as > HW default values, include mt2712 and mt7622. > > Those RC device work fine with all I have tried EP device except that > the portdrv was not attached to those device. But no scenario need those > service as far as I know. > > > Out of curiosity, can you show the "lspci -vv" output for the device > > and the downstream devices of interest? > > > lspci only read the class type 0604h, it does not care about the > subordinate values of the class type. I will put the "lspci -vv" output > at bottom of this mail. > > > Do you happen to know whether this functionality is configurable, > > e.g., is there some way software can enable or disable subtractive > > decode? I assume this would be some device-specific thing, because I > > can't find anything in the Bridge Control register or similar. The > > PCIe spec doesn't even contain the word "subtractive". > > Those class type values for Mediatek's RC has a register which could be > used to change its values. We never touch this backdoor register since > without the portdrv attached is fine, nobody ask for the port service > yet. > > I did some homework for the subtractive decode PCI-to-PCI bridge, and > did not found much more information about that. I guess those port > service should also support subtractive bridge since spec does not > forbidden that. OK, I guess that makes sense. > > The "PCI Express to PCI/PCI-X Bridge Specification", r1.0, says a PCI > > Express bridge (which would include Root Ports and Switch Ports) has a > > Class Code of 0x060400 (Non-Subtractive PCI-PCI Bridge) (sec 1.1). > > > > Sec 1.3.4 says subtractive decode on the primary interface is "not > > applicable or outside the scope of this spec". > # lspci -vvv > 00:01.0 Class 0604: Device 14c3:5396 > ... > > > Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> > > > --- > > > drivers/pci/pcie/portdrv_pci.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c > > > index eef22dc..86926ea 100644 > > > --- a/drivers/pci/pcie/portdrv_pci.c > > > +++ b/drivers/pci/pcie/portdrv_pci.c > > > @@ -179,7 +179,7 @@ static void pcie_portdrv_err_resume(struct pci_dev *dev) > > > */ > > > static const struct pci_device_id port_pci_ids[] = { { > > > /* handle any PCI-Express port */ > > > - PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0), > > > + PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0x01), Can you please rework this slightly so it leaves the original entry alone and just *adds* a new entry that matches the subtractive-decode bridges? I think that will make it more obvious what's changing. > > > }, { /* end: all zeroes */ } > > > };
diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c index eef22dc..86926ea 100644 --- a/drivers/pci/pcie/portdrv_pci.c +++ b/drivers/pci/pcie/portdrv_pci.c @@ -179,7 +179,7 @@ static void pcie_portdrv_err_resume(struct pci_dev *dev) */ static const struct pci_device_id port_pci_ids[] = { { /* handle any PCI-Express port */ - PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0), + PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0x01), }, { /* end: all zeroes */ } };