| Message ID | 20190213095613.31045-1-benjamin.gaignard@linaro.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | ARM errata 814220 | expand |
On Wed, Feb 13, 2019 at 10:56 AM Benjamin Gaignard <benjamin.gaignard@linaro.org> wrote: > > Implement ARM errata 814220 for Cortex A7. > > This patch has been wroten by Jason Liu years ago but never send upstream. > I have tried to contact the author on multiple email addresses but I haven't > found any valid one... > I have keep Jason's sign-off and just rebase the patch on to v5-rc6. > > Benjamin Gaignard (2): > ARM: errata 814220-B-Cache maintenance by set/way operations can > execute out of order. > ARM: stm32: select ARM errata 814220 > > arch/arm/Kconfig | 10 ++++++++++ > arch/arm/mach-stm32/Kconfig | 1 + > arch/arm/mm/cache-v7.S | 3 +++ > 3 files changed, 14 insertions(+) Looks good to me, Acked-by: Arnd Bergmann <arnd@arndb.de> It probably makes most sense to keep them as a series, either through the soc tree or Russell's patch tracker, so feel free to add it there, and have them both in the stm32 soc branch for arm-soc if Russell prefers. As we have a number of Cortex-A7 based platforms with all kinds of revisions, I wonder if we should also select the workaround for the others. I can probably figure out which SoC platforms are based on Cortex-A7, but I have no idea about the revisions, so that might mean we'd have to do it for all of them. According to the latest TRM I found, only revisions r0p0 through r0p5 exist, and the erraturm text lists r0p2 through r0p5, which may mean all products ever shipped in practice (the oldest public TRM from 2012 already describe r0p3). Arnd
On 2/13/19 3:52 PM, Arnd Bergmann wrote: > On Wed, Feb 13, 2019 at 10:56 AM Benjamin Gaignard > <benjamin.gaignard@linaro.org> wrote: >> >> Implement ARM errata 814220 for Cortex A7. >> >> This patch has been wroten by Jason Liu years ago but never send upstream. >> I have tried to contact the author on multiple email addresses but I haven't >> found any valid one... >> I have keep Jason's sign-off and just rebase the patch on to v5-rc6. >> >> Benjamin Gaignard (2): >> ARM: errata 814220-B-Cache maintenance by set/way operations can >> execute out of order. >> ARM: stm32: select ARM errata 814220 >> >> arch/arm/Kconfig | 10 ++++++++++ >> arch/arm/mach-stm32/Kconfig | 1 + >> arch/arm/mm/cache-v7.S | 3 +++ >> 3 files changed, 14 insertions(+) > > Looks good to me, > > Acked-by: Arnd Bergmann <arnd@arndb.de> > > It probably makes most sense to keep them as a series, either > through the soc tree or Russell's patch tracker, so feel free to add > it there, and have them both in the stm32 soc branch for arm-soc > if Russell prefers. Russel, what do you think about Arnd proposition? I could take both patches in my stm32 tree. It'll make part of future v5.2 pull request. Alex > > As we have a number of Cortex-A7 based platforms with all > kinds of revisions, I wonder if we should also select the workaround > for the others. I can probably figure out which SoC platforms > are based on Cortex-A7, but I have no idea about the revisions, > so that might mean we'd have to do it for all of them. According > to the latest TRM I found, only revisions r0p0 through r0p5 > exist, and the erraturm text lists r0p2 through r0p5, which may > mean all products ever shipped in practice (the oldest public > TRM from 2012 already describe r0p3). > > > > > Arnd >
Implement ARM errata 814220 for Cortex A7. This patch has been wroten by Jason Liu years ago but never send upstream. I have tried to contact the author on multiple email addresses but I haven't found any valid one... I have keep Jason's sign-off and just rebase the patch on to v5-rc6. Benjamin Gaignard (2): ARM: errata 814220-B-Cache maintenance by set/way operations can execute out of order. ARM: stm32: select ARM errata 814220 arch/arm/Kconfig | 10 ++++++++++ arch/arm/mach-stm32/Kconfig | 1 + arch/arm/mm/cache-v7.S | 3 +++ 3 files changed, 14 insertions(+)