| Message ID | 20190213095613.31045-2-benjamin.gaignard@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM errata 814220 | expand |
On Wed, Feb 13, 2019 at 10:56:12AM +0100, Benjamin Gaignard wrote: > Description: > The v7 ARM states that all cache and branch predictor maintenance operations > that do not specify an address execute, relative to each other, in program > order. However, because of this erratum, an L2 set/way cache maintenance > operation can overtake an L1 set/way cache maintenance operation, this would > cause the data corruption. > > This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5. > > This patch is the SW workaround by adding a DSB before changing cache levels as > the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation. > > Signed-off-by: Jason Liu <r64343@freescale.com> > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> > --- > arch/arm/Kconfig | 10 ++++++++++ > arch/arm/mm/cache-v7.S | 3 +++ > 2 files changed, 13 insertions(+) > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 664e918e2624..6f608558e22a 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -1227,6 +1227,16 @@ config PCI_HOST_ITE8152 > default y > select DMABOUNCE > > +config ARM_ERRATA_814220 > + bool "ARM errata: Cache maintenance by set/way operations can execute out of order" > + depends on CPU_V7 > + help > + The v7 ARM states that all cache and branch predictor maintenance operations > + that do not specify an address execute, relative to each other, in program order. > + However, because of this erratum, an L2 set/way cache maintenance operation can > + overtake an L1 set/way cache maintenance operation. This ERRATA only affected the > + Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5. We generally try to keep help lines so that when edited on an 80 column display, they do not wrap. Please can you reformat the above to satisfy that please? (means breaking the lines after "maintenance" on the first line.) Thanks. > + > endmenu > > menu "Kernel Features" > diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S > index 2149b47a0c5a..7ff7b4c197cc 100644 > --- a/arch/arm/mm/cache-v7.S > +++ b/arch/arm/mm/cache-v7.S > @@ -163,6 +163,9 @@ loop2: > skip: > add r10, r10, #2 @ increment cache number > cmp r3, r10 > +#ifdef CONFIG_ARM_ERRATA_814220 > + dsb > +#endif > bgt flush_levels > finished: > mov r10, #0 @ switch back to cache level 0 > -- > 2.15.0 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 664e918e2624..6f608558e22a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1227,6 +1227,16 @@ config PCI_HOST_ITE8152 default y select DMABOUNCE +config ARM_ERRATA_814220 + bool "ARM errata: Cache maintenance by set/way operations can execute out of order" + depends on CPU_V7 + help + The v7 ARM states that all cache and branch predictor maintenance operations + that do not specify an address execute, relative to each other, in program order. + However, because of this erratum, an L2 set/way cache maintenance operation can + overtake an L1 set/way cache maintenance operation. This ERRATA only affected the + Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5. + endmenu menu "Kernel Features" diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 2149b47a0c5a..7ff7b4c197cc 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -163,6 +163,9 @@ loop2: skip: add r10, r10, #2 @ increment cache number cmp r3, r10 +#ifdef CONFIG_ARM_ERRATA_814220 + dsb +#endif bgt flush_levels finished: mov r10, #0 @ switch back to cache level 0