| Message ID | 1550084693-9797-6-git-send-email-abel.vesa@nxp.com (mailing list archive) |
|---|---|
| State | RFC |
| Headers | show |
| Series | Add cpufreq-dt support i.MX8MQ | expand |
Hi Abel Am Mittwoch, den 13.02.2019, 19:05 +0000 schrieb Abel Vesa: > Add the opp table containing only non over drive opps. > Also add the cpu-supply nodes for the A53 cores in the EVK board. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 17 +++++++++++++++++ > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++++++++++++++++++++++ > 2 files changed, 40 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > index 54737bf..114359e 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > @@ -31,6 +31,23 @@ > gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; > enable-active-high; > }; > + > +}; > + > +&A53_0 { > + cpu-supply = <&sw1a_reg>; > +}; > + > +&A53_1 { > + cpu-supply = <&sw1a_reg>; > +}; > + > +&A53_2 { > + cpu-supply = <&sw1a_reg>; > +}; > + > +&A53_3 { > + cpu-supply = <&sw1a_reg>; > }; This should be a separate patch. And AFAICS this is wrong, sw1a on the MX8M-EVK is the GPU supply, the CPU is supplied by a dedicated switcher that is controlled via a GPIO. Regards, Lucas > &fec1 { > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 1a89062..89b2d5f 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -91,6 +91,7 @@ > clocks = <&clk IMX8MQ_CLK_ARM>; > enable-method = "psci"; > next-level-cache = <&A53_L2>; > + operating-points-v2 = <&a53_0_opp_table>; > }; > > A53_1: cpu@1 { > @@ -101,6 +102,7 @@ > clocks = <&clk IMX8MQ_CLK_ARM>; > enable-method = "psci"; > next-level-cache = <&A53_L2>; > + operating-points-v2 = <&a53_0_opp_table>; > }; > > A53_2: cpu@2 { > @@ -111,6 +113,7 @@ > clocks = <&clk IMX8MQ_CLK_ARM>; > enable-method = "psci"; > next-level-cache = <&A53_L2>; > + operating-points-v2 = <&a53_0_opp_table>; > }; > > A53_3: cpu@3 { > @@ -121,6 +124,7 @@ > clocks = <&clk IMX8MQ_CLK_ARM>; > enable-method = "psci"; > next-level-cache = <&A53_L2>; > + operating-points-v2 = <&a53_0_opp_table>; > }; > > A53_L2: l2-cache0 { > @@ -666,6 +670,25 @@ > status = "disabled"; > }; > > + > + a53_0_opp_table: opp-table { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-800000000 { > + opp-hz = /bits/ 64 <800000000>; > + opp-microvolt = <900000>; > + clock-latency-ns = <150000>; > + }; > + > + opp-1000000000 { > + opp-hz = /bits/ 64 <1000000000>; > + opp-microvolt = <900000>; > + clock-latency-ns = <150000>; > + opp-suspend; > + }; > + }; > + > gic: interrupt-controller@38800000 { > compatible = "arm,gic-v3"; > reg = <0x38800000 0x10000>, /* GIC > Dist */
On 19-02-14 16:50:28, Lucas Stach wrote: > Hi Abel > > Am Mittwoch, den 13.02.2019, 19:05 +0000 schrieb Abel Vesa: > > Add the opp table containing only non over drive opps. > > Also add the cpu-supply nodes for the A53 cores in the EVK board. > > > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > > --- > > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 17 +++++++++++++++++ > > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++++++++++++++++++++++ > > 2 files changed, 40 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > index 54737bf..114359e 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > @@ -31,6 +31,23 @@ > > gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; > > enable-active-high; > > }; > > + > > +}; > > + > > +&A53_0 { > > + cpu-supply = <&sw1a_reg>; > > +}; > > + > > +&A53_1 { > > + cpu-supply = <&sw1a_reg>; > > +}; > > + > > +&A53_2 { > > + cpu-supply = <&sw1a_reg>; > > +}; > > + > > +&A53_3 { > > + cpu-supply = <&sw1a_reg>; > > }; > > This should be a separate patch. > OK, will send as separate patches in the next version. > And AFAICS this is wrong, sw1a on the MX8M-EVK is the GPU supply, the > CPU is supplied by a dedicated switcher that is controlled via a GPIO. > Hmm, I think you're right. At least this is what the following document says. https://www.mouser.com/ds/2/302/IMX8MDQLQEVKHUG-1280333.pdf So I guess this means there will not be any cpu-supply properties. Thanks, Abel > Regards, > Lucas > > > &fec1 { > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > index 1a89062..89b2d5f 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > @@ -91,6 +91,7 @@ > > clocks = <&clk IMX8MQ_CLK_ARM>; > > enable-method = "psci"; > > next-level-cache = <&A53_L2>; > > + operating-points-v2 = <&a53_0_opp_table>; > > }; > > > > A53_1: cpu@1 { > > @@ -101,6 +102,7 @@ > > clocks = <&clk IMX8MQ_CLK_ARM>; > > enable-method = "psci"; > > next-level-cache = <&A53_L2>; > > + operating-points-v2 = <&a53_0_opp_table>; > > }; > > > > A53_2: cpu@2 { > > @@ -111,6 +113,7 @@ > > clocks = <&clk IMX8MQ_CLK_ARM>; > > enable-method = "psci"; > > next-level-cache = <&A53_L2>; > > + operating-points-v2 = <&a53_0_opp_table>; > > }; > > > > A53_3: cpu@3 { > > @@ -121,6 +124,7 @@ > > clocks = <&clk IMX8MQ_CLK_ARM>; > > enable-method = "psci"; > > next-level-cache = <&A53_L2>; > > + operating-points-v2 = <&a53_0_opp_table>; > > }; > > > > A53_L2: l2-cache0 { > > @@ -666,6 +670,25 @@ > > status = "disabled"; > > }; > > > > + > > + a53_0_opp_table: opp-table { > > + compatible = "operating-points-v2"; > > + opp-shared; > > + > > + opp-800000000 { > > + opp-hz = /bits/ 64 <800000000>; > > + opp-microvolt = <900000>; > > + clock-latency-ns = <150000>; > > + }; > > + > > + opp-1000000000 { > > + opp-hz = /bits/ 64 <1000000000>; > > + opp-microvolt = <900000>; > > + clock-latency-ns = <150000>; > > + opp-suspend; > > + }; > > + }; > > + > > gic: interrupt-controller@38800000 { > > compatible = "arm,gic-v3"; > > reg = <0x38800000 0x10000>, /* GIC > > Dist */
Am Donnerstag, den 14.02.2019, 17:18 +0000 schrieb Abel Vesa: > On 19-02-14 16:50:28, Lucas Stach wrote: > > Hi Abel > > > > Am Mittwoch, den 13.02.2019, 19:05 +0000 schrieb Abel Vesa: > > > Add the opp table containing only non over drive opps. > > > Also add the cpu-supply nodes for the A53 cores in the EVK board. > > > > > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > > > --- > > > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 17 > > > +++++++++++++++++ > > > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 > > > +++++++++++++++++++++++ > > > 2 files changed, 40 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > > b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > > index 54737bf..114359e 100644 > > > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > > @@ -31,6 +31,23 @@ > > > gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; > > > enable-active-high; > > > }; > > > + > > > +}; > > > + > > > +&A53_0 { > > > + cpu-supply = <&sw1a_reg>; > > > +}; > > > + > > > +&A53_1 { > > > + cpu-supply = <&sw1a_reg>; > > > +}; > > > + > > > +&A53_2 { > > > + cpu-supply = <&sw1a_reg>; > > > +}; > > > + > > > +&A53_3 { > > > + cpu-supply = <&sw1a_reg>; > > > }; > > > > This should be a separate patch. > > > > OK, will send as separate patches in the next version. > > > And AFAICS this is wrong, sw1a on the MX8M-EVK is the GPU supply, > > the > > CPU is supplied by a dedicated switcher that is controlled via a > > GPIO. > > > > Hmm, I think you're right. At least this is what the following > document says. > > https://www.mouser.com/ds/2/302/IMX8MDQLQEVKHUG-1280333.pdf > > So I guess this means there will not be any cpu-supply properties. There is a variable voltage CPU supply, but you need to model it as a gpio-regulator in the DT, it's not part of the PMIC provided rails. Regards, Lucas
Am Donnerstag, den 14.02.2019, 18:26 +0100 schrieb Lucas Stach: > Am Donnerstag, den 14.02.2019, 17:18 +0000 schrieb Abel Vesa: > > On 19-02-14 16:50:28, Lucas Stach wrote: > > > Hi Abel > > > > > > Am Mittwoch, den 13.02.2019, 19:05 +0000 schrieb Abel Vesa: > > > > Add the opp table containing only non over drive opps. > > > > Also add the cpu-supply nodes for the A53 cores in the EVK > > > > board. > > > > > > > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > > > > --- > > > > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 17 > > > > +++++++++++++++++ > > > > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 > > > > +++++++++++++++++++++++ > > > > 2 files changed, 40 insertions(+) > > > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > > > b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > > > index 54737bf..114359e 100644 > > > > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > > > @@ -31,6 +31,23 @@ > > > > gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; > > > > enable-active-high; > > > > }; > > > > + > > > > +}; > > > > + > > > > +&A53_0 { > > > > + cpu-supply = <&sw1a_reg>; > > > > +}; > > > > + > > > > +&A53_1 { > > > > + cpu-supply = <&sw1a_reg>; > > > > +}; > > > > + > > > > +&A53_2 { > > > > + cpu-supply = <&sw1a_reg>; > > > > +}; > > > > + > > > > +&A53_3 { > > > > + cpu-supply = <&sw1a_reg>; > > > > }; > > > > > > This should be a separate patch. > > > > > > > OK, will send as separate patches in the next version. > > > > > And AFAICS this is wrong, sw1a on the MX8M-EVK is the GPU supply, > > > the > > > CPU is supplied by a dedicated switcher that is controlled via a > > > GPIO. > > > > > > > Hmm, I think you're right. At least this is what the following > > document says. > > > > https://www.mouser.com/ds/2/302/IMX8MDQLQEVKHUG-1280333.pdf > > > > So I guess this means there will not be any cpu-supply properties. > > There is a variable voltage CPU supply, but you need to model it as a > gpio-regulator in the DT, it's not part of the PMIC provided rails. In the schematics it's the line called PWM_LED (actually it's just GPIO1_IO13) that controls the voltage. This changes the feedback of the DCDC switcher, so it can toggle between 0.9V and 1.0V. Regards, Lucas
On 19-02-14 18:32:40, Lucas Stach wrote: > Am Donnerstag, den 14.02.2019, 18:26 +0100 schrieb Lucas Stach: > > Am Donnerstag, den 14.02.2019, 17:18 +0000 schrieb Abel Vesa: > > > On 19-02-14 16:50:28, Lucas Stach wrote: > > > > Hi Abel > > > > > > > > Am Mittwoch, den 13.02.2019, 19:05 +0000 schrieb Abel Vesa: > > > > > Add the opp table containing only non over drive opps. > > > > > Also add the cpu-supply nodes for the A53 cores in the EVK > > > > > board. > > > > > > > > > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > > > > > --- > > > > > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 17 > > > > > +++++++++++++++++ > > > > > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 > > > > > +++++++++++++++++++++++ > > > > > 2 files changed, 40 insertions(+) > > > > > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > > > > b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > > > > index 54737bf..114359e 100644 > > > > > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > > > > @@ -31,6 +31,23 @@ > > > > > gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; > > > > > enable-active-high; > > > > > }; > > > > > + > > > > > +}; > > > > > + > > > > > +&A53_0 { > > > > > + cpu-supply = <&sw1a_reg>; > > > > > +}; > > > > > + > > > > > +&A53_1 { > > > > > + cpu-supply = <&sw1a_reg>; > > > > > +}; > > > > > + > > > > > +&A53_2 { > > > > > + cpu-supply = <&sw1a_reg>; > > > > > +}; > > > > > + > > > > > +&A53_3 { > > > > > + cpu-supply = <&sw1a_reg>; > > > > > }; > > > > > > > > This should be a separate patch. > > > > > > > > > > OK, will send as separate patches in the next version. > > > > > > > And AFAICS this is wrong, sw1a on the MX8M-EVK is the GPU supply, > > > > the > > > > CPU is supplied by a dedicated switcher that is controlled via a > > > > GPIO. > > > > > > > > > > Hmm, I think you're right. At least this is what the following > > > document says. > > > > > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.mouser.com%2Fds%2F2%2F302%2FIMX8MDQLQEVKHUG-1280333.pdf&data=02%7C01%7Cabel.vesa%40nxp.com%7Cf7666164aff84f6f975d08d692a26c2a%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C636857623628438873&sdata=EJJdfD8ewEXVQSTf2FqjEeUqGJd%2BwW94OQag428lszY%3D&reserved=0 > > > > > > So I guess this means there will not be any cpu-supply properties. > > > > There is a variable voltage CPU supply, but you need to model it as a > > gpio-regulator in the DT, it's not part of the PMIC provided rails. > > In the schematics it's the line called PWM_LED (actually it's just > GPIO1_IO13) that controls the voltage. This changes the feedback of the > DCDC switcher, so it can toggle between 0.9V and 1.0V. > Thanks, will look into it tomorrow when I get back at the office. > Regards, > Lucas
On 2019-02-13 11:05, Abel Vesa wrote: > Add the opp table containing only non over drive opps. > Also add the cpu-supply nodes for the A53 cores in the EVK board. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 17 +++++++++++++++++ > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 > +++++++++++++++++++++++ > 2 files changed, 40 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > index 54737bf..114359e 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > @@ -31,6 +31,23 @@ > gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; > enable-active-high; > }; > + > +}; > + > +&A53_0 { > + cpu-supply = <&sw1a_reg>; > +}; > + > +&A53_1 { > + cpu-supply = <&sw1a_reg>; > +}; > + > +&A53_2 { > + cpu-supply = <&sw1a_reg>; > +}; > + > +&A53_3 { > + cpu-supply = <&sw1a_reg>; > }; > > &fec1 { > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 1a89062..89b2d5f 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -91,6 +91,7 @@ > clocks = <&clk IMX8MQ_CLK_ARM>; > enable-method = "psci"; > next-level-cache = <&A53_L2>; > + operating-points-v2 = <&a53_0_opp_table>; > }; > > A53_1: cpu@1 { > @@ -101,6 +102,7 @@ > clocks = <&clk IMX8MQ_CLK_ARM>; > enable-method = "psci"; > next-level-cache = <&A53_L2>; > + operating-points-v2 = <&a53_0_opp_table>; > }; > > A53_2: cpu@2 { > @@ -111,6 +113,7 @@ > clocks = <&clk IMX8MQ_CLK_ARM>; > enable-method = "psci"; > next-level-cache = <&A53_L2>; > + operating-points-v2 = <&a53_0_opp_table>; > }; > > A53_3: cpu@3 { > @@ -121,6 +124,7 @@ > clocks = <&clk IMX8MQ_CLK_ARM>; > enable-method = "psci"; > next-level-cache = <&A53_L2>; > + operating-points-v2 = <&a53_0_opp_table>; > }; > > A53_L2: l2-cache0 { > @@ -666,6 +670,25 @@ > status = "disabled"; > }; > > + > + a53_0_opp_table: opp-table { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-800000000 { > + opp-hz = /bits/ 64 <800000000>; > + opp-microvolt = <900000>; > + clock-latency-ns = <150000>; > + }; > + > + opp-1000000000 { > + opp-hz = /bits/ 64 <1000000000>; > + opp-microvolt = <900000>; Shouldn't this be opp-microvolt = <1000000>; > + clock-latency-ns = <150000>; > + opp-suspend; > + }; > + }; > + > gic: interrupt-controller@38800000 { > compatible = "arm,gic-v3"; > reg = <0x38800000 0x10000>, /* GIC Dist */
On 19-02-14 16:55:22, Angus Ainslie wrote: > On 2019-02-13 11:05, Abel Vesa wrote: > > Add the opp table containing only non over drive opps. > > Also add the cpu-supply nodes for the A53 cores in the EVK board. > > > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > > --- > > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 17 +++++++++++++++++ > > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 > > +++++++++++++++++++++++ > > 2 files changed, 40 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > index 54737bf..114359e 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > > @@ -31,6 +31,23 @@ > > gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; > > enable-active-high; > > }; > > + > > +}; > > + > > +&A53_0 { > > + cpu-supply = <&sw1a_reg>; > > +}; > > + > > +&A53_1 { > > + cpu-supply = <&sw1a_reg>; > > +}; > > + > > +&A53_2 { > > + cpu-supply = <&sw1a_reg>; > > +}; > > + > > +&A53_3 { > > + cpu-supply = <&sw1a_reg>; > > }; > > > > &fec1 { > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > index 1a89062..89b2d5f 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > @@ -91,6 +91,7 @@ > > clocks = <&clk IMX8MQ_CLK_ARM>; > > enable-method = "psci"; > > next-level-cache = <&A53_L2>; > > + operating-points-v2 = <&a53_0_opp_table>; > > }; > > > > A53_1: cpu@1 { > > @@ -101,6 +102,7 @@ > > clocks = <&clk IMX8MQ_CLK_ARM>; > > enable-method = "psci"; > > next-level-cache = <&A53_L2>; > > + operating-points-v2 = <&a53_0_opp_table>; > > }; > > > > A53_2: cpu@2 { > > @@ -111,6 +113,7 @@ > > clocks = <&clk IMX8MQ_CLK_ARM>; > > enable-method = "psci"; > > next-level-cache = <&A53_L2>; > > + operating-points-v2 = <&a53_0_opp_table>; > > }; > > > > A53_3: cpu@3 { > > @@ -121,6 +124,7 @@ > > clocks = <&clk IMX8MQ_CLK_ARM>; > > enable-method = "psci"; > > next-level-cache = <&A53_L2>; > > + operating-points-v2 = <&a53_0_opp_table>; > > }; > > > > A53_L2: l2-cache0 { > > @@ -666,6 +670,25 @@ > > status = "disabled"; > > }; > > > > + > > + a53_0_opp_table: opp-table { > > + compatible = "operating-points-v2"; > > + opp-shared; > > + > > + opp-800000000 { > > + opp-hz = /bits/ 64 <800000000>; > > + opp-microvolt = <900000>; > > + clock-latency-ns = <150000>; > > + }; > > + > > + opp-1000000000 { > > + opp-hz = /bits/ 64 <1000000000>; > > + opp-microvolt = <900000>; > > Shouldn't this be > > opp-microvolt = <1000000>; > Hmm, I looked into some older datasheet which said the maximum non overdrive is 1GHz. But the latest one I could find: https://www.nxp.com/docs/en/data-sheet/IMX8MDQLQIEC.pdf says it's 0.8GHz. So I'll fix it in the next version. Thanks. > > + clock-latency-ns = <150000>; > > + opp-suspend; > > + }; > > + }; > > + > > gic: interrupt-controller@38800000 { > > compatible = "arm,gic-v3"; > > reg = <0x38800000 0x10000>, /* GIC Dist */ >
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 54737bf..114359e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -31,6 +31,23 @@ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; + +}; + +&A53_0 { + cpu-supply = <&sw1a_reg>; +}; + +&A53_1 { + cpu-supply = <&sw1a_reg>; +}; + +&A53_2 { + cpu-supply = <&sw1a_reg>; +}; + +&A53_3 { + cpu-supply = <&sw1a_reg>; }; &fec1 { diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 1a89062..89b2d5f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -91,6 +91,7 @@ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_0_opp_table>; }; A53_1: cpu@1 { @@ -101,6 +102,7 @@ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_0_opp_table>; }; A53_2: cpu@2 { @@ -111,6 +113,7 @@ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_0_opp_table>; }; A53_3: cpu@3 { @@ -121,6 +124,7 @@ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_0_opp_table>; }; A53_L2: l2-cache0 { @@ -666,6 +670,25 @@ status = "disabled"; }; + + a53_0_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000>; + clock-latency-ns = <150000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <900000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */
Add the opp table containing only non over drive opps. Also add the cpu-supply nodes for the A53 cores in the EVK board. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 17 +++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++++++++++++++++++++++ 2 files changed, 40 insertions(+)