| Message ID | 1549296944-17285-3-git-send-email-jcrouse@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/msm: Improved a6xx GMU reset | expand |
On Mon, Feb 4, 2019 at 10:15 AM Jordan Crouse <jcrouse@codeaurora.org> wrote: > > The GMU should have two power domains defined: "cx" and "gx". "cx" is the > actual power domain for the device and "gx" will be attached at runtime > to manage reference counting on the GPU device in case of a GMU crash. power-domains are supposed to be actual regions on a chip die which can be power gated. However, they are often abused by being defined in terms of kernel PM domains which are not always the same thing. This description sounds like the latter case. Rob
On Sun, Feb 17, 2019 at 4:08 PM Rob Herring <robh+dt@kernel.org> wrote: > > On Mon, Feb 4, 2019 at 10:15 AM Jordan Crouse <jcrouse@codeaurora.org> wrote: > > > > The GMU should have two power domains defined: "cx" and "gx". "cx" is the > > actual power domain for the device and "gx" will be attached at runtime > > to manage reference counting on the GPU device in case of a GMU crash. > > power-domains are supposed to be actual regions on a chip die which > can be power gated. However, they are often abused by being defined in > terms of kernel PM domains which are not always the same thing. This > description sounds like the latter case. > iirc (and Jordan can correct me), this arrangement was needed because normally the GMU does the GPU power control (except for if we manage to crash it and need to reset the GMU).. so maybe not 100% about the actual regions on chip die which can be gated.. but it is a reality of how hw + fw + sw fit together.. BR, -R
On Sun, Feb 17, 2019 at 05:43:16PM -0500, Rob Clark wrote: > On Sun, Feb 17, 2019 at 4:08 PM Rob Herring <robh+dt@kernel.org> wrote: > > > > On Mon, Feb 4, 2019 at 10:15 AM Jordan Crouse <jcrouse@codeaurora.org> wrote: > > > > > > The GMU should have two power domains defined: "cx" and "gx". "cx" is the > > > actual power domain for the device and "gx" will be attached at runtime > > > to manage reference counting on the GPU device in case of a GMU crash. > > > > power-domains are supposed to be actual regions on a chip die which > > can be power gated. However, they are often abused by being defined in > > terms of kernel PM domains which are not always the same thing. This > > description sounds like the latter case. > > > > iirc (and Jordan can correct me), this arrangement was needed because > normally the GMU does the GPU power control (except for if we manage > to crash it and need to reset the GMU).. > > so maybe not 100% about the actual regions on chip die which can be > gated.. but it is a reality of how hw + fw + sw fit together.. Ack - forgot to add Stephen who knows about this. Rob is correct. The GX domain is real but it is normally controlled by an off-CPU microcontroller. The CPU needs to get involved only when the microcontroller crashes and we need to get things back to normal. So the description of it being an actual region on a chip die is accurate. It sounds like I need to describe the hardware better in the bindings document. Jordan
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt b/Documentation/devicetree/bindings/display/msm/gmu.txt index 3439b38..90af5b0 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.txt +++ b/Documentation/devicetree/bindings/display/msm/gmu.txt @@ -24,7 +24,10 @@ Required properties: * "cxo" * "axi" * "mnoc" -- power-domains: should be <&clock_gpucc GPU_CX_GDSC> +- power-domains: should be: + <&clock_gpucc GPU_CX_GDSC> + <&clock_gpucc GPU_GX_GDSC> +- power-domain-names: Matching names for the power domains - iommus: phandle to the adreno iommu - operating-points-v2: phandle to the OPP operating points @@ -51,7 +54,10 @@ Example: <&gcc GCC_GPU_MEMNOC_GFX_CLK>; clock-names = "gmu", "cxo", "axi", "memnoc"; - power-domains = <&gpucc GPU_CX_GDSC>; + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", "gx"; + iommus = <&adreno_smmu 5>; operating-points-v2 = <&gmu_opp_table>;
The GMU should have two power domains defined: "cx" and "gx". "cx" is the actual power domain for the device and "gx" will be attached at runtime to manage reference counting on the GPU device in case of a GMU crash. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> --- Documentation/devicetree/bindings/display/msm/gmu.txt | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)