| Message ID | 1551504025-3541-1-git-send-email-skomatineni@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [V1,01/11] mmc: tegra: fix ddr signaling for non-ddr modes | expand |
Hi Sowjanya, On 02/03/2019 05:20, Sowjanya Komatineni wrote: > ddr_signaling is set to true for DDR50 and DDR52 modes but is > not set back to false for other modes. This programs incorrect > host clock when mode change happens from DDR52/DDR50 to other > SDR or HS modes like incase of mmc_retune where it switches > from HS400 to HS DDR and then from HS DDR to HS mode and then > to HS200. > > This patch fixes the ddr_signaling to set properly for non DDR > modes. > > Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> > --- > drivers/mmc/host/sdhci-tegra.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c > index 32e62904c0d3..46086dd43bfb 100644 > --- a/drivers/mmc/host/sdhci-tegra.c > +++ b/drivers/mmc/host/sdhci-tegra.c > @@ -779,6 +779,7 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, > bool set_dqs_trim = false; > bool do_hs400_dll_cal = false; > > + tegra_host->ddr_signaling = false; > switch (timing) { > case MMC_TIMING_UHS_SDR50: > case MMC_TIMING_UHS_SDR104: I have tested this series on Tegra210, Tegra186 and Tegra194 and see no further issues. Thanks for getting this out! Feel free to add my ... Tested-by: Jon Hunter <jonathanh@nvidia.com> Cheers Jon
On 2/03/19 7:20 AM, Sowjanya Komatineni wrote: > ddr_signaling is set to true for DDR50 and DDR52 modes but is > not set back to false for other modes. This programs incorrect > host clock when mode change happens from DDR52/DDR50 to other > SDR or HS modes like incase of mmc_retune where it switches > from HS400 to HS DDR and then from HS DDR to HS mode and then > to HS200. > > This patch fixes the ddr_signaling to set properly for non DDR > modes. > > Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> > --- > drivers/mmc/host/sdhci-tegra.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c > index 32e62904c0d3..46086dd43bfb 100644 > --- a/drivers/mmc/host/sdhci-tegra.c > +++ b/drivers/mmc/host/sdhci-tegra.c > @@ -779,6 +779,7 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, > bool set_dqs_trim = false; > bool do_hs400_dll_cal = false; > > + tegra_host->ddr_signaling = false; > switch (timing) { > case MMC_TIMING_UHS_SDR50: > case MMC_TIMING_UHS_SDR104: >
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 32e62904c0d3..46086dd43bfb 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -779,6 +779,7 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, bool set_dqs_trim = false; bool do_hs400_dll_cal = false; + tegra_host->ddr_signaling = false; switch (timing) { case MMC_TIMING_UHS_SDR50: case MMC_TIMING_UHS_SDR104:
ddr_signaling is set to true for DDR50 and DDR52 modes but is not set back to false for other modes. This programs incorrect host clock when mode change happens from DDR52/DDR50 to other SDR or HS modes like incase of mmc_retune where it switches from HS400 to HS DDR and then from HS DDR to HS mode and then to HS200. This patch fixes the ddr_signaling to set properly for non DDR modes. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- drivers/mmc/host/sdhci-tegra.c | 1 + 1 file changed, 1 insertion(+)