| Message ID | 1551865835-50974-7-git-send-email-bibby.hsieh@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | support gce on mt8183 platform | expand |
Hi, Bibby: On Wed, 2019-03-06 at 17:50 +0800, Bibby Hsieh wrote: > GCE hardware stored event information in own internal sysram, > if the initial value in those sysram is not zero value > it will cause a situation that gce can wait the event immediately > after client ask gce to wait event but not really trigger the > corresponding hardware. > > In order to make sure that the wait event function is > exactly correct, we need to clear the sysram value in > cmdq initial flow. > > Fixup commit 623a6143a845 ("mailbox: mediatek: Add Mediatek CMDQ driver") Please refer to [1] for the fix tag. [1] https://www.kernel.org/doc/html/v5.0/process/submitting-patches.html Regards, CK > > Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> > --- > drivers/mailbox/mtk-cmdq-mailbox.c | 5 +++++ > include/linux/mailbox/mtk-cmdq-mailbox.h | 2 ++ > include/linux/soc/mediatek/mtk-cmdq.h | 3 --- > 3 files changed, 7 insertions(+), 3 deletions(-) > > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c > index 6db1e2d..4e744cf 100644 > --- a/drivers/mailbox/mtk-cmdq-mailbox.c > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c > @@ -33,6 +33,7 @@ > #define CMDQ_THR_END_ADDR 0x24 > #define CMDQ_THR_WAIT_TOKEN 0x30 > #define CMDQ_THR_PRIORITY 0x40 > +#define CMDQ_SYNC_TOKEN_UPDATE 0x68 > > #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 > #define CMDQ_THR_ENABLED 0x1 > @@ -103,8 +104,12 @@ static void cmdq_thread_resume(struct cmdq_thread *thread) > > static void cmdq_init(struct cmdq *cmdq) > { > + int i; > + > WARN_ON(clk_enable(cmdq->clock) < 0); > writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); > + for (i = 0; i <= CMDQ_MAX_EVENT; i++) > + writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); > clk_disable(cmdq->clock); > } > > diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h > index ccb7342..911475da 100644 > --- a/include/linux/mailbox/mtk-cmdq-mailbox.h > +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h > @@ -19,6 +19,8 @@ > #define CMDQ_WFE_UPDATE BIT(31) > #define CMDQ_WFE_WAIT BIT(15) > #define CMDQ_WFE_WAIT_VALUE 0x1 > +/** cmdq event maximum */ > +#define CMDQ_MAX_EVENT 0x3ff > > /* > * CMDQ_CODE_MASK: > diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h > index 54ade13..4e88999 100644 > --- a/include/linux/soc/mediatek/mtk-cmdq.h > +++ b/include/linux/soc/mediatek/mtk-cmdq.h > @@ -13,9 +13,6 @@ > > #define CMDQ_NO_TIMEOUT 0xffffffffu > > -/** cmdq event maximum */ > -#define CMDQ_MAX_EVENT 0x3ff > - > struct cmdq_pkt; > > struct cmdq_client {
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index 6db1e2d..4e744cf 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -33,6 +33,7 @@ #define CMDQ_THR_END_ADDR 0x24 #define CMDQ_THR_WAIT_TOKEN 0x30 #define CMDQ_THR_PRIORITY 0x40 +#define CMDQ_SYNC_TOKEN_UPDATE 0x68 #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 #define CMDQ_THR_ENABLED 0x1 @@ -103,8 +104,12 @@ static void cmdq_thread_resume(struct cmdq_thread *thread) static void cmdq_init(struct cmdq *cmdq) { + int i; + WARN_ON(clk_enable(cmdq->clock) < 0); writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); + for (i = 0; i <= CMDQ_MAX_EVENT; i++) + writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); clk_disable(cmdq->clock); } diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h index ccb7342..911475da 100644 --- a/include/linux/mailbox/mtk-cmdq-mailbox.h +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h @@ -19,6 +19,8 @@ #define CMDQ_WFE_UPDATE BIT(31) #define CMDQ_WFE_WAIT BIT(15) #define CMDQ_WFE_WAIT_VALUE 0x1 +/** cmdq event maximum */ +#define CMDQ_MAX_EVENT 0x3ff /* * CMDQ_CODE_MASK: diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 54ade13..4e88999 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -13,9 +13,6 @@ #define CMDQ_NO_TIMEOUT 0xffffffffu -/** cmdq event maximum */ -#define CMDQ_MAX_EVENT 0x3ff - struct cmdq_pkt; struct cmdq_client {
GCE hardware stored event information in own internal sysram, if the initial value in those sysram is not zero value it will cause a situation that gce can wait the event immediately after client ask gce to wait event but not really trigger the corresponding hardware. In order to make sure that the wait event function is exactly correct, we need to clear the sysram value in cmdq initial flow. Fixup commit 623a6143a845 ("mailbox: mediatek: Add Mediatek CMDQ driver") Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> --- drivers/mailbox/mtk-cmdq-mailbox.c | 5 +++++ include/linux/mailbox/mtk-cmdq-mailbox.h | 2 ++ include/linux/soc/mediatek/mtk-cmdq.h | 3 --- 3 files changed, 7 insertions(+), 3 deletions(-)