| Message ID | 1552275991-34648-10-git-send-email-hsin-hsiung.wang@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Support for MediaTek PMIC MT6358 | expand |
On Mon, 2019-03-11 at 11:46 +0800, Hsin-Hsiung Wang wrote: > From: Ran Bi <ran.bi@mediatek.com> > > This add support for the MediaTek MT6358 RTC. MT6397 mfd will pass > RTC_WRTGR address offset to RTC driver. > > Signed-off-by: Ran Bi <ran.bi@mediatek.com> > --- > drivers/rtc/rtc-mt6397.c | 16 ++++++++++++++-- > 1 file changed, 14 insertions(+), 2 deletions(-) > > diff --git a/drivers/rtc/rtc-mt6397.c b/drivers/rtc/rtc-mt6397.c > index f85f1fc..c8a0090 100644 > --- a/drivers/rtc/rtc-mt6397.c > +++ b/drivers/rtc/rtc-mt6397.c > @@ -27,7 +27,7 @@ > #define RTC_BBPU 0x0000 > #define RTC_BBPU_CBUSY BIT(6) > > -#define RTC_WRTGR 0x003c > +#define RTC_WRTGR_DEFAULT 0x003c > > #define RTC_IRQ_STA 0x0002 > #define RTC_IRQ_STA_AL BIT(0) > @@ -78,6 +78,7 @@ struct mt6397_rtc { > struct regmap *regmap; > int irq; > u32 addr_base; > + u32 wrtgr_offset; It is strange that hardware change trigger register offset, I think we have no choice to add a field to describe it. > }; > > static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc) > @@ -86,7 +87,8 @@ static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc) > int ret; > u32 data; > > - ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_WRTGR, 1); > + ret = regmap_write(rtc->regmap, > + rtc->addr_base + rtc->wrtgr_offset, 1); > if (ret < 0) > return ret; > > @@ -341,6 +343,15 @@ static int mtk_rtc_probe(struct platform_device *pdev) > res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > rtc->addr_base = res->start; > > + res = platform_get_resource(pdev, IORESOURCE_REG, 0); > + if (res) { > + rtc->wrtgr_offset = res->start; > + dev_info(&pdev->dev, "register offset:%d\n", rtc->wrtgr_offset); Nit: useless log > + } else { > + rtc->wrtgr_offset = RTC_WRTGR_DEFAULT; > + dev_err(&pdev->dev, "Failed to get register offset\n"); > + } > + > rtc->irq = platform_get_irq(pdev, 0); > if (rtc->irq < 0) > return rtc->irq; > @@ -420,6 +431,7 @@ static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_rtc_suspend, > mt6397_rtc_resume); > > static const struct of_device_id mt6397_rtc_of_match[] = { > + { .compatible = "mediatek,mt6358-rtc", }, > { .compatible = "mediatek,mt6397-rtc", }, > { } > }; Without the log, you can my get Acked-by: Eddie Huang <eddie.huang@mediatekcom>
Hi, Should use 'rtc: mt6397: ' as prefix for this patch. On Mon, 2019-03-11 at 11:46 +0800, Hsin-Hsiung Wang wrote: > From: Ran Bi <ran.bi@mediatek.com> > > This add support for the MediaTek MT6358 RTC. MT6397 mfd will pass > RTC_WRTGR address offset to RTC driver. > > Signed-off-by: Ran Bi <ran.bi@mediatek.com> > --- > drivers/rtc/rtc-mt6397.c | 16 ++++++++++++++-- > 1 file changed, 14 insertions(+), 2 deletions(-) > > diff --git a/drivers/rtc/rtc-mt6397.c b/drivers/rtc/rtc-mt6397.c > index f85f1fc..c8a0090 100644 > --- a/drivers/rtc/rtc-mt6397.c > +++ b/drivers/rtc/rtc-mt6397.c > @@ -27,7 +27,7 @@ > #define RTC_BBPU 0x0000 > #define RTC_BBPU_CBUSY BIT(6) > > -#define RTC_WRTGR 0x003c > +#define RTC_WRTGR_DEFAULT 0x003c > > #define RTC_IRQ_STA 0x0002 > #define RTC_IRQ_STA_AL BIT(0) > @@ -78,6 +78,7 @@ struct mt6397_rtc { > struct regmap *regmap; > int irq; > u32 addr_base; > + u32 wrtgr_offset; > }; > > static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc) > @@ -86,7 +87,8 @@ static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc) > int ret; > u32 data; > > - ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_WRTGR, 1); > + ret = regmap_write(rtc->regmap, > + rtc->addr_base + rtc->wrtgr_offset, 1); > if (ret < 0) > return ret; > > @@ -341,6 +343,15 @@ static int mtk_rtc_probe(struct platform_device *pdev) > res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > rtc->addr_base = res->start; > > + res = platform_get_resource(pdev, IORESOURCE_REG, 0); > + if (res) { > + rtc->wrtgr_offset = res->start; > + dev_info(&pdev->dev, "register offset:%d\n", rtc->wrtgr_offset); > + } else { > + rtc->wrtgr_offset = RTC_WRTGR_DEFAULT; > + dev_err(&pdev->dev, "Failed to get register offset\n"); > + } > + Since this will be passed by MFD, do we still need to keep the DEFAULT? Any case this platform_get_resource will failed? It's too bad HW changed this offset, but I'm not sure about passing this information from MFD. We have 1 register that have different offset now, and might have others for future chips, adding each one by IORESOURCE_IRQ doesn't looks like a good solution. Keeping this information in RTC driver only also looks better. Joe.C
On 21/03/2019 17:51:26+0800, Yingjoe Chen wrote: > > Hi, > > > Should use 'rtc: mt6397: ' as prefix for this patch. > > > On Mon, 2019-03-11 at 11:46 +0800, Hsin-Hsiung Wang wrote: > > From: Ran Bi <ran.bi@mediatek.com> > > > > This add support for the MediaTek MT6358 RTC. MT6397 mfd will pass > > RTC_WRTGR address offset to RTC driver. > > > > Signed-off-by: Ran Bi <ran.bi@mediatek.com> > > --- > > drivers/rtc/rtc-mt6397.c | 16 ++++++++++++++-- > > 1 file changed, 14 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/rtc/rtc-mt6397.c b/drivers/rtc/rtc-mt6397.c > > index f85f1fc..c8a0090 100644 > > --- a/drivers/rtc/rtc-mt6397.c > > +++ b/drivers/rtc/rtc-mt6397.c > > @@ -27,7 +27,7 @@ > > #define RTC_BBPU 0x0000 > > #define RTC_BBPU_CBUSY BIT(6) > > > > -#define RTC_WRTGR 0x003c > > +#define RTC_WRTGR_DEFAULT 0x003c > > > > #define RTC_IRQ_STA 0x0002 > > #define RTC_IRQ_STA_AL BIT(0) > > @@ -78,6 +78,7 @@ struct mt6397_rtc { > > struct regmap *regmap; > > int irq; > > u32 addr_base; > > + u32 wrtgr_offset; > > }; > > > > static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc) > > @@ -86,7 +87,8 @@ static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc) > > int ret; > > u32 data; > > > > - ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_WRTGR, 1); > > + ret = regmap_write(rtc->regmap, > > + rtc->addr_base + rtc->wrtgr_offset, 1); > > if (ret < 0) > > return ret; > > > > @@ -341,6 +343,15 @@ static int mtk_rtc_probe(struct platform_device *pdev) > > res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > rtc->addr_base = res->start; > > > > + res = platform_get_resource(pdev, IORESOURCE_REG, 0); > > + if (res) { > > + rtc->wrtgr_offset = res->start; > > + dev_info(&pdev->dev, "register offset:%d\n", rtc->wrtgr_offset); > > + } else { > > + rtc->wrtgr_offset = RTC_WRTGR_DEFAULT; > > + dev_err(&pdev->dev, "Failed to get register offset\n"); > > + } > > + > > Since this will be passed by MFD, do we still need to keep the DEFAULT? > Any case this platform_get_resource will failed? > > It's too bad HW changed this offset, but I'm not sure about passing this > information from MFD. We have 1 register that have different offset now, > and might have others for future chips, adding each one by > IORESOURCE_IRQ doesn't looks like a good solution. Keeping this > information in RTC driver only also looks better. > I agree, this would be better.
diff --git a/drivers/rtc/rtc-mt6397.c b/drivers/rtc/rtc-mt6397.c index f85f1fc..c8a0090 100644 --- a/drivers/rtc/rtc-mt6397.c +++ b/drivers/rtc/rtc-mt6397.c @@ -27,7 +27,7 @@ #define RTC_BBPU 0x0000 #define RTC_BBPU_CBUSY BIT(6) -#define RTC_WRTGR 0x003c +#define RTC_WRTGR_DEFAULT 0x003c #define RTC_IRQ_STA 0x0002 #define RTC_IRQ_STA_AL BIT(0) @@ -78,6 +78,7 @@ struct mt6397_rtc { struct regmap *regmap; int irq; u32 addr_base; + u32 wrtgr_offset; }; static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc) @@ -86,7 +87,8 @@ static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc) int ret; u32 data; - ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_WRTGR, 1); + ret = regmap_write(rtc->regmap, + rtc->addr_base + rtc->wrtgr_offset, 1); if (ret < 0) return ret; @@ -341,6 +343,15 @@ static int mtk_rtc_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); rtc->addr_base = res->start; + res = platform_get_resource(pdev, IORESOURCE_REG, 0); + if (res) { + rtc->wrtgr_offset = res->start; + dev_info(&pdev->dev, "register offset:%d\n", rtc->wrtgr_offset); + } else { + rtc->wrtgr_offset = RTC_WRTGR_DEFAULT; + dev_err(&pdev->dev, "Failed to get register offset\n"); + } + rtc->irq = platform_get_irq(pdev, 0); if (rtc->irq < 0) return rtc->irq; @@ -420,6 +431,7 @@ static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_rtc_suspend, mt6397_rtc_resume); static const struct of_device_id mt6397_rtc_of_match[] = { + { .compatible = "mediatek,mt6358-rtc", }, { .compatible = "mediatek,mt6397-rtc", }, { } };