diff mbox series

[libdrm] tests/amdgpu: minor fix for dispatch/draw test

Message ID 1553050000-7288-1-git-send-email-flora.cui@amd.com (mailing list archive)
State New, archived
Headers show
Series [libdrm] tests/amdgpu: minor fix for dispatch/draw test | expand

Commit Message

Flora Cui March 20, 2019, 2:46 a.m. UTC
1. clear cmd buffer
2. make amdgpu_memcpy_dispatch_test static
3. tab/space fix

Change-Id: Idf55f8881f66458b585092eccb55b6042520e4ad
Signed-off-by: Flora Cui <flora.cui@amd.com>
---
 tests/amdgpu/basic_tests.c | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

Comments

Alex Deucher March 21, 2019, 2:41 a.m. UTC | #1
On Tue, Mar 19, 2019 at 10:47 PM Cui, Flora <Flora.Cui@amd.com> wrote:
>
> 1. clear cmd buffer
> 2. make amdgpu_memcpy_dispatch_test static
> 3. tab/space fix
>
> Change-Id: Idf55f8881f66458b585092eccb55b6042520e4ad
> Signed-off-by: Flora Cui <flora.cui@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

and pushed.

Thanks!

> ---
>  tests/amdgpu/basic_tests.c | 20 ++++++++++++--------
>  1 file changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
> index a364f67..2d47269 100644
> --- a/tests/amdgpu/basic_tests.c
> +++ b/tests/amdgpu/basic_tests.c
> @@ -2177,6 +2177,7 @@ static void amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
>                                         &bo_cmd, (void **)&ptr_cmd,
>                                         &mc_address_cmd, &va_cmd);
>         CU_ASSERT_EQUAL(r, 0);
> +       memset(ptr_cmd, 0, bo_cmd_size);
>
>         r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
>                                         AMDGPU_GEM_DOMAIN_VRAM, 0,
> @@ -2227,7 +2228,7 @@ static void amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
>         ptr_cmd[i++] = 1;
>
>         while (i & 7)
> -               ptr_cmd[i++] =  0xffff1000; /* type3 nop packet */
> +               ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
>
>         resources[0] = bo_dst;
>         resources[1] = bo_shader;
> @@ -2283,9 +2284,9 @@ static void amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
>         CU_ASSERT_EQUAL(r, 0);
>  }
>
> -void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
> -                                uint32_t ip_type,
> -                                uint32_t ring)
> +static void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
> +                                       uint32_t ip_type,
> +                                       uint32_t ring)
>  {
>         amdgpu_context_handle context_handle;
>         amdgpu_bo_handle bo_src, bo_dst, bo_shader, bo_cmd, resources[4];
> @@ -2313,6 +2314,7 @@ void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
>                                     &bo_cmd, (void **)&ptr_cmd,
>                                     &mc_address_cmd, &va_cmd);
>         CU_ASSERT_EQUAL(r, 0);
> +       memset(ptr_cmd, 0, bo_cmd_size);
>
>         r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
>                                         AMDGPU_GEM_DOMAIN_VRAM, 0,
> @@ -2371,7 +2373,7 @@ void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
>         ptr_cmd[i++] = 1;
>
>         while (i & 7)
> -               ptr_cmd[i++] =  0xffff1000; /* type3 nop packet */
> +               ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
>
>         resources[0] = bo_shader;
>         resources[1] = bo_src;
> @@ -2799,7 +2801,8 @@ void amdgpu_memset_draw(amdgpu_device_handle device_handle,
>                                         AMDGPU_GEM_DOMAIN_GTT, 0,
>                                         &bo_cmd, (void **)&ptr_cmd,
>                                         &mc_address_cmd, &va_cmd);
> -        CU_ASSERT_EQUAL(r, 0);
> +       CU_ASSERT_EQUAL(r, 0);
> +       memset(ptr_cmd, 0, bo_cmd_size);
>
>         r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
>                                         AMDGPU_GEM_DOMAIN_VRAM, 0,
> @@ -2828,7 +2831,7 @@ void amdgpu_memset_draw(amdgpu_device_handle device_handle,
>         i += amdgpu_draw_draw(ptr_cmd + i);
>
>         while (i & 7)
> -               ptr_cmd[i++] =  0xffff1000; /* type3 nop packet */
> +               ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
>
>         resources[0] = bo_dst;
>         resources[1] = bo_shader_ps;
> @@ -2952,6 +2955,7 @@ static void amdgpu_memcpy_draw(amdgpu_device_handle device_handle,
>                                     &bo_cmd, (void **)&ptr_cmd,
>                                     &mc_address_cmd, &va_cmd);
>         CU_ASSERT_EQUAL(r, 0);
> +       memset(ptr_cmd, 0, bo_cmd_size);
>
>         r = amdgpu_bo_alloc_and_map(device_handle, bo_size, 4096,
>                                         AMDGPU_GEM_DOMAIN_VRAM, 0,
> @@ -2999,7 +3003,7 @@ static void amdgpu_memcpy_draw(amdgpu_device_handle device_handle,
>         i += amdgpu_draw_draw(ptr_cmd + i);
>
>         while (i & 7)
> -               ptr_cmd[i++] =  0xffff1000; /* type3 nop packet */
> +               ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
>
>         resources[0] = bo_dst;
>         resources[1] = bo_src;
> --
> 2.7.4
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
diff mbox series

Patch

diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index a364f67..2d47269 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -2177,6 +2177,7 @@  static void amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
 					&bo_cmd, (void **)&ptr_cmd,
 					&mc_address_cmd, &va_cmd);
 	CU_ASSERT_EQUAL(r, 0);
+	memset(ptr_cmd, 0, bo_cmd_size);
 
 	r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
 					AMDGPU_GEM_DOMAIN_VRAM, 0,
@@ -2227,7 +2228,7 @@  static void amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
 	ptr_cmd[i++] = 1;
 
 	while (i & 7)
-		ptr_cmd[i++] =  0xffff1000; /* type3 nop packet */
+		ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
 
 	resources[0] = bo_dst;
 	resources[1] = bo_shader;
@@ -2283,9 +2284,9 @@  static void amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
 	CU_ASSERT_EQUAL(r, 0);
 }
 
-void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
-				 uint32_t ip_type,
-				 uint32_t ring)
+static void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
+					uint32_t ip_type,
+					uint32_t ring)
 {
 	amdgpu_context_handle context_handle;
 	amdgpu_bo_handle bo_src, bo_dst, bo_shader, bo_cmd, resources[4];
@@ -2313,6 +2314,7 @@  void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
 				    &bo_cmd, (void **)&ptr_cmd,
 				    &mc_address_cmd, &va_cmd);
 	CU_ASSERT_EQUAL(r, 0);
+	memset(ptr_cmd, 0, bo_cmd_size);
 
 	r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
 					AMDGPU_GEM_DOMAIN_VRAM, 0,
@@ -2371,7 +2373,7 @@  void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
 	ptr_cmd[i++] = 1;
 
 	while (i & 7)
-		ptr_cmd[i++] =  0xffff1000; /* type3 nop packet */
+		ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
 
 	resources[0] = bo_shader;
 	resources[1] = bo_src;
@@ -2799,7 +2801,8 @@  void amdgpu_memset_draw(amdgpu_device_handle device_handle,
 					AMDGPU_GEM_DOMAIN_GTT, 0,
 					&bo_cmd, (void **)&ptr_cmd,
 					&mc_address_cmd, &va_cmd);
-        CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(r, 0);
+	memset(ptr_cmd, 0, bo_cmd_size);
 
 	r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
 					AMDGPU_GEM_DOMAIN_VRAM, 0,
@@ -2828,7 +2831,7 @@  void amdgpu_memset_draw(amdgpu_device_handle device_handle,
 	i += amdgpu_draw_draw(ptr_cmd + i);
 
 	while (i & 7)
-		ptr_cmd[i++] =  0xffff1000; /* type3 nop packet */
+		ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
 
 	resources[0] = bo_dst;
 	resources[1] = bo_shader_ps;
@@ -2952,6 +2955,7 @@  static void amdgpu_memcpy_draw(amdgpu_device_handle device_handle,
 				    &bo_cmd, (void **)&ptr_cmd,
 				    &mc_address_cmd, &va_cmd);
 	CU_ASSERT_EQUAL(r, 0);
+	memset(ptr_cmd, 0, bo_cmd_size);
 
 	r = amdgpu_bo_alloc_and_map(device_handle, bo_size, 4096,
 					AMDGPU_GEM_DOMAIN_VRAM, 0,
@@ -2999,7 +3003,7 @@  static void amdgpu_memcpy_draw(amdgpu_device_handle device_handle,
 	i += amdgpu_draw_draw(ptr_cmd + i);
 
 	while (i & 7)
-		ptr_cmd[i++] =  0xffff1000; /* type3 nop packet */
+		ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
 
 	resources[0] = bo_dst;
 	resources[1] = bo_src;