[1/9] drm/i915: rename raw reg access functions

Message ID	20190325214940.23632-2-daniele.ceraolospurio@intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <intel-gfx-bounces@lists.freedesktop.org> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> To: intel-gfx@lists.freedesktop.org Date: Mon, 25 Mar 2019 14:49:32 -0700 Message-Id: <20190325214940.23632-2-daniele.ceraolospurio@intel.com> In-Reply-To: <20190325214940.23632-1-daniele.ceraolospurio@intel.com> References: <20190325214940.23632-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/9] drm/i915: rename raw reg access functions Precedence: list Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	more uncore rework \| expand [0/9] more uncore rework [1/9] drm/i915: rename raw reg access functions [2/9] drm/i915: add HAS_FORCEWAKE flag to uncore [3/9] drm/i915: add uncore flags for unclaimed mmio [4/9] drm/i915: take a ref to the rpm in the uncore structure [5/9] drm/i915: switch uncore mmio funcs to use intel_uncore [6/9] drm/i915: switch intel_uncore_forcewake_for_reg to intel_uncore [7/9] drm/i915: intel_wait_for_register_fw to uncore [8/9] drm/i915: switch intel_wait_for_register to uncore [9/9] drm/i915: take a reference to uncore in the engine and use it

Message ID

20190325214940.23632-2-daniele.ceraolospurio@intel.com (mailing list archive)

State

New, archived

Headers

From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
To: intel-gfx@lists.freedesktop.org
Date: Mon, 25 Mar 2019 14:49:32 -0700
Message-Id: <20190325214940.23632-2-daniele.ceraolospurio@intel.com>
In-Reply-To: <20190325214940.23632-1-daniele.ceraolospurio@intel.com>
References: <20190325214940.23632-1-daniele.ceraolospurio@intel.com>
MIME-Version: 1.0
Subject: [Intel-gfx] [PATCH 1/9] drm/i915: rename raw reg access functions
Precedence: list
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: base64
Errors-To: intel-gfx-bounces@lists.freedesktop.org
Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>

Series

more uncore rework | expand

Commit Message

Daniele Ceraolo Spurio March 25, 2019, 9:49 p.m. UTC

They now work on uncore, so use raw_uncore_ prefix. Also move them to
uncore.h

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_drv.h     | 32 ++-----------------
 drivers/gpu/drm/i915/i915_vgpu.c    |  6 ++--
 drivers/gpu/drm/i915/intel_uncore.c | 48 ++++++++++++++---------------
 drivers/gpu/drm/i915/intel_uncore.h | 27 ++++++++++++++++
 4 files changed, 57 insertions(+), 56 deletions(-)

Comments

Zanoni, Paulo R March 25, 2019, 10:41 p.m. UTC | #1

Em seg, 2019-03-25 às 14:49 -0700, Daniele Ceraolo Spurio escreveu:
> They now work on uncore, so use raw_uncore_ prefix. Also move them to
> uncore.h
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/i915_drv.h     | 32 ++-----------------
>  drivers/gpu/drm/i915/i915_vgpu.c    |  6 ++--
>  drivers/gpu/drm/i915/intel_uncore.c | 48 ++++++++++++++---------------
>  drivers/gpu/drm/i915/intel_uncore.h | 27 ++++++++++++++++
>  4 files changed, 57 insertions(+), 56 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4e30f7b19b51..558d40f07ffe 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3507,32 +3507,6 @@ static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
>  #define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
>  #define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)
>  
> -#define __raw_read(x, s) \
> -static inline uint##x##_t __raw_i915_read##x(const struct intel_uncore *uncore, \
> -					     i915_reg_t reg) \
> -{ \
> -	return read##s(uncore->regs + i915_mmio_reg_offset(reg)); \
> -}
> -
> -#define __raw_write(x, s) \
> -static inline void __raw_i915_write##x(const struct intel_uncore *uncore, \
> -				       i915_reg_t reg, uint##x##_t val) \
> -{ \
> -	write##s(val, uncore->regs + i915_mmio_reg_offset(reg)); \
> -}
> -__raw_read(8, b)
> -__raw_read(16, w)
> -__raw_read(32, l)
> -__raw_read(64, q)
> -
> -__raw_write(8, b)
> -__raw_write(16, w)
> -__raw_write(32, l)
> -__raw_write(64, q)
> -
> -#undef __raw_read
> -#undef __raw_write
> -
>  /* These are untraced mmio-accessors that are only valid to be used inside
>   * critical sections, such as inside IRQ handlers, where forcewake is explicitly
>   * controlled.
> @@ -3559,9 +3533,9 @@ __raw_write(64, q)
>   * therefore generally be serialised, by either the dev_priv->uncore.lock or
>   * a more localised lock guarding all access to that bank of registers.
>   */
> -#define I915_READ_FW(reg__) __raw_i915_read32(&dev_priv->uncore, (reg__))
> -#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(&dev_priv->uncore, (reg__), (val__))
> -#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(&dev_priv->uncore, (reg__), (val__))
> +#define I915_READ_FW(reg__) __raw_uncore_read32(&dev_priv->uncore, (reg__))
> +#define I915_WRITE_FW(reg__, val__) __raw_uncore_write32(&dev_priv->uncore, (reg__), (val__))
> +#define I915_WRITE64_FW(reg__, val__) __raw_uncore_write64(&dev_priv->uncore, (reg__), (val__))
>  #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
>  
>  /* "Broadcast RGB" property */
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
> index 3d0b493e4200..94d3992b599d 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -66,17 +66,17 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
>  
>  	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
>  
> -	magic = __raw_i915_read64(uncore, vgtif_reg(magic));
> +	magic = __raw_uncore_read64(uncore, vgtif_reg(magic));
>  	if (magic != VGT_MAGIC)
>  		return;
>  
> -	version_major = __raw_i915_read16(uncore, vgtif_reg(version_major));
> +	version_major = __raw_uncore_read16(uncore, vgtif_reg(version_major));
>  	if (version_major < VGT_VERSION_MAJOR) {
>  		DRM_INFO("VGT interface version mismatch!\n");
>  		return;
>  	}
>  
> -	dev_priv->vgpu.caps = __raw_i915_read32(uncore, vgtif_reg(vgt_caps));
> +	dev_priv->vgpu.caps = __raw_uncore_read32(uncore, vgtif_reg(vgt_caps));
>  
>  	dev_priv->vgpu.active = true;
>  	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 1816eeae3ba9..3f74889c4212 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -31,7 +31,7 @@
>  #define FORCEWAKE_ACK_TIMEOUT_MS 50
>  #define GT_FIFO_TIMEOUT_MS	 10
>  
> -#define __raw_posting_read(uncore__, reg__) (void)__raw_i915_read32((uncore__), (reg__))
> +#define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))

Now the person trying to figure out what __raw_posting_read() does will
have to chase __raw_uncore_read32(), which is not even greppable. I'm
not sure this is an improvement to our codebase, but the neatness of
just passing everything does have some value. Not really a big deal, so
I'm not blocking merging on this.


>  
>  static const char * const forcewake_domain_names[] = {
>  	"render",
> @@ -279,7 +279,7 @@ static inline u32 gt_thread_status(struct intel_uncore *uncore)
>  {
>  	u32 val;
>  
> -	val = __raw_i915_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
> +	val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
>  	val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
>  
>  	return val;
> @@ -306,7 +306,7 @@ static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
>  
>  static inline u32 fifo_free_entries(struct intel_uncore *uncore)
>  {
> -	u32 count = __raw_i915_read32(uncore, GTFIFOCTL);
> +	u32 count = __raw_uncore_read32(uncore, GTFIFOCTL);
>  
>  	return count & GT_FIFO_FREE_ENTRIES_MASK;
>  }
> @@ -451,7 +451,7 @@ static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
>  	if (IS_HASWELL(dev_priv) ||
>  	    IS_BROADWELL(dev_priv) ||
>  	    INTEL_GEN(dev_priv) >= 9) {
> -		dev_priv->edram_cap = __raw_i915_read32(&dev_priv->uncore,
> +		dev_priv->edram_cap = __raw_uncore_read32(&dev_priv->uncore,
>  							HSW_EDRAM_CAP);

Indentation is now broken for this line above.


With those 2 super important details addressed or not:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

>  
>  		/* NB: We can't write IDICR yet because we do not have gt funcs
> @@ -470,11 +470,11 @@ fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
>  {
>  	u32 dbg;
>  
> -	dbg = __raw_i915_read32(uncore, FPGA_DBG);
> +	dbg = __raw_uncore_read32(uncore, FPGA_DBG);
>  	if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
>  		return false;
>  
> -	__raw_i915_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
> +	__raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
>  
>  	return true;
>  }
> @@ -484,11 +484,11 @@ vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
>  {
>  	u32 cer;
>  
> -	cer = __raw_i915_read32(uncore, CLAIM_ER);
> +	cer = __raw_uncore_read32(uncore, CLAIM_ER);
>  	if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
>  		return false;
>  
> -	__raw_i915_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
> +	__raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
>  
>  	return true;
>  }
> @@ -498,11 +498,11 @@ gen6_check_for_fifo_debug(struct intel_uncore *uncore)
>  {
>  	u32 fifodbg;
>  
> -	fifodbg = __raw_i915_read32(uncore, GTFIFODBG);
> +	fifodbg = __raw_uncore_read32(uncore, GTFIFODBG);
>  
>  	if (unlikely(fifodbg)) {
>  		DRM_DEBUG_DRIVER("GTFIFODBG = 0x08%x\n", fifodbg);
> -		__raw_i915_write32(uncore, GTFIFODBG, fifodbg);
> +		__raw_uncore_write32(uncore, GTFIFODBG, fifodbg);
>  	}
>  
>  	return fifodbg;
> @@ -537,10 +537,10 @@ static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
>  
>  	/* WaDisableShadowRegForCpd:chv */
>  	if (IS_CHERRYVIEW(i915)) {
> -		__raw_i915_write32(uncore, GTFIFOCTL,
> -				   __raw_i915_read32(uncore, GTFIFOCTL) |
> -				   GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
> -				   GT_FIFO_CTL_RC6_POLICY_STALL);
> +		__raw_uncore_write32(uncore, GTFIFOCTL,
> +				     __raw_uncore_read32(uncore, GTFIFOCTL) |
> +				     GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
> +				     GT_FIFO_CTL_RC6_POLICY_STALL);
>  	}
>  
>  	iosf_mbi_punit_acquire();
> @@ -1068,7 +1068,7 @@ ilk_dummy_write(struct intel_uncore *uncore)
>  	/* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
>  	 * the chip from rc6 before touching it for real. MI_MODE is masked,
>  	 * hence harmless to write 0 into. */
> -	__raw_i915_write32(uncore, MI_MODE, 0);
> +	__raw_uncore_write32(uncore, MI_MODE, 0);
>  }
>  
>  static void
> @@ -1110,7 +1110,7 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
>  static u##x \
>  gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
>  	GEN2_READ_HEADER(x); \
> -	val = __raw_i915_read##x(uncore, reg); \
> +	val = __raw_uncore_read##x(uncore, reg); \
>  	GEN2_READ_FOOTER; \
>  }
>  
> @@ -1119,7 +1119,7 @@ static u##x \
>  gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
>  	GEN2_READ_HEADER(x); \
>  	ilk_dummy_write(uncore); \
> -	val = __raw_i915_read##x(uncore, reg); \
> +	val = __raw_uncore_read##x(uncore, reg); \
>  	GEN2_READ_FOOTER; \
>  }
>  
> @@ -1189,7 +1189,7 @@ func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) {
>  	fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
>  	if (fw_engine) \
>  		__force_wake_auto(uncore, fw_engine); \
> -	val = __raw_i915_read##x(uncore, reg); \
> +	val = __raw_uncore_read##x(uncore, reg); \
>  	GEN6_READ_FOOTER; \
>  }
>  #define __gen6_read(x) __gen_read(gen6, x)
> @@ -1226,7 +1226,7 @@ __gen6_read(64)
>  static void \
>  gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
>  	GEN2_WRITE_HEADER; \
> -	__raw_i915_write##x(uncore, reg, val); \
> +	__raw_uncore_write##x(uncore, reg, val); \
>  	GEN2_WRITE_FOOTER; \
>  }
>  
> @@ -1235,7 +1235,7 @@ static void \
>  gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
>  	GEN2_WRITE_HEADER; \
>  	ilk_dummy_write(uncore); \
> -	__raw_i915_write##x(uncore, reg, val); \
> +	__raw_uncore_write##x(uncore, reg, val); \
>  	GEN2_WRITE_FOOTER; \
>  }
>  
> @@ -1271,7 +1271,7 @@ gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool
>  	GEN6_WRITE_HEADER; \
>  	if (NEEDS_FORCE_WAKE(offset)) \
>  		__gen6_gt_wait_for_fifo(uncore); \
> -	__raw_i915_write##x(uncore, reg, val); \
> +	__raw_uncore_write##x(uncore, reg, val); \
>  	GEN6_WRITE_FOOTER; \
>  }
>  
> @@ -1283,7 +1283,7 @@ func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, boo
>  	fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
>  	if (fw_engine) \
>  		__force_wake_auto(uncore, fw_engine); \
> -	__raw_i915_write##x(uncore, reg, val); \
> +	__raw_uncore_write##x(uncore, reg, val); \
>  	GEN6_WRITE_FOOTER; \
>  }
>  #define __gen8_write(x) __gen_write(gen8, x)
> @@ -1470,7 +1470,7 @@ static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
>  		 * before the ecobus check.
>  		 */
>  
> -		__raw_i915_write32(uncore, FORCEWAKE, 0);
> +		__raw_uncore_write32(uncore, FORCEWAKE, 0);
>  		__raw_posting_read(uncore, ECOBUS);
>  
>  		fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
> @@ -1478,7 +1478,7 @@ static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
>  
>  		spin_lock_irq(&uncore->lock);
>  		fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
> -		ecobus = __raw_i915_read32(uncore, ECOBUS);
> +		ecobus = __raw_uncore_read32(uncore, ECOBUS);
>  		fw_domains_put(uncore, FORCEWAKE_RENDER);
>  		spin_unlock_irq(&uncore->lock);
>  
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index d345e5ab04a5..f7670cbc41c9 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -215,6 +215,33 @@ int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
>  					    2, timeout_ms, NULL);
>  }
>  
> +/* register access functions */
> +#define __raw_read(x__, s__) \
> +static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
> +					    i915_reg_t reg) \
> +{ \
> +	return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
> +}
> +
> +#define __raw_write(x__, s__) \
> +static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
> +					   i915_reg_t reg, u##x__ val) \
> +{ \
> +	write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
> +}
> +__raw_read(8, b)
> +__raw_read(16, w)
> +__raw_read(32, l)
> +__raw_read(64, q)
> +
> +__raw_write(8, b)
> +__raw_write(16, w)
> +__raw_write(32, l)
> +__raw_write(64, q)
> +
> +#undef __raw_read
> +#undef __raw_write
> +
>  #define raw_reg_read(base, reg) \
>  	readl(base + i915_mmio_reg_offset(reg))
>  #define raw_reg_write(base, reg, value) \

Chris Wilson March 25, 2019, 10:57 p.m. UTC | #2

Quoting Paulo Zanoni (2019-03-25 22:41:55)
> Em seg, 2019-03-25 às 14:49 -0700, Daniele Ceraolo Spurio escreveu:
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > index 1816eeae3ba9..3f74889c4212 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -31,7 +31,7 @@
> >  #define FORCEWAKE_ACK_TIMEOUT_MS 50
> >  #define GT_FIFO_TIMEOUT_MS    10
> >  
> > -#define __raw_posting_read(uncore__, reg__) (void)__raw_i915_read32((uncore__), (reg__))
> > +#define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
> 
> Now the person trying to figure out what __raw_posting_read() does will
> have to chase __raw_uncore_read32(), which is not even greppable. I'm
> not sure this is an improvement to our codebase, but the neatness of
> just passing everything does have some value. Not really a big deal, so
> I'm not blocking merging on this.

By the time you get down to __raw_versions, you should have established the
pattern in the higher level functions to figure out that by this point
this is just a convenient wrapper around readl. I hope.

Note, you can kill __raw_posting_read() which should help.
-Chris

kernel test robot March 26, 2019, 4:18 a.m. UTC | #3

Hi Daniele,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20190325]
[cannot apply to v5.1-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Daniele-Ceraolo-Spurio/more-uncore-rework/20190326-110805
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x003-201912 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All error/warnings (new ones prefixed by >>):

    ^~~~~~~~~~
   In file included from include/linux/io.h:25:0,
                    from include/linux/io-mapping.h:24,
                    from drivers/gpu/drm/i915/i915_vma.h:28,
                    from drivers/gpu/drm/i915/intel_guc.h:36,
                    from drivers/gpu/drm/i915/intel_guc.c:25:
   arch/x86/include/asm/io.h:59:17: error: conflicting types for 'readl'
    build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
                    ^
   arch/x86/include/asm/io.h:48:20: note: in definition of macro 'build_mmio_read'
    static inline type name(const volatile void __iomem *addr) \
                       ^~~~
   In file included from drivers/gpu/drm/i915/intel_guc.h:28:0,
                    from drivers/gpu/drm/i915/intel_guc.c:25:
   drivers/gpu/drm/i915/intel_uncore.h:223:9: note: previous implicit declaration of 'readl' was here
     return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
            ^
   drivers/gpu/drm/i915/intel_uncore.h:234:1: note: in expansion of macro '__raw_read'
    __raw_read(32, l)
    ^~~~~~~~~~
   In file included from include/linux/io.h:25:0,
                    from include/linux/io-mapping.h:24,
                    from drivers/gpu/drm/i915/i915_vma.h:28,
                    from drivers/gpu/drm/i915/intel_guc.h:36,
                    from drivers/gpu/drm/i915/intel_guc.c:25:
   arch/x86/include/asm/io.h:65:18: warning: conflicting types for 'writeb'
    build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
                     ^
   arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
    static inline void name(type val, volatile void __iomem *addr) \
                       ^~~~
   arch/x86/include/asm/io.h:65:18: error: static declaration of 'writeb' follows non-static declaration
    build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
                     ^
   arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
    static inline void name(type val, volatile void __iomem *addr) \
                       ^~~~
   In file included from drivers/gpu/drm/i915/intel_guc.h:28:0,
                    from drivers/gpu/drm/i915/intel_guc.c:25:
   drivers/gpu/drm/i915/intel_uncore.h:230:2: note: previous implicit declaration of 'writeb' was here
     write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
     ^
   drivers/gpu/drm/i915/intel_uncore.h:237:1: note: in expansion of macro '__raw_write'
    __raw_write(8, b)
    ^~~~~~~~~~~
   In file included from include/linux/io.h:25:0,
                    from include/linux/io-mapping.h:24,
                    from drivers/gpu/drm/i915/i915_vma.h:28,
                    from drivers/gpu/drm/i915/intel_guc.h:36,
                    from drivers/gpu/drm/i915/intel_guc.c:25:
   arch/x86/include/asm/io.h:66:18: warning: conflicting types for 'writew'
    build_mmio_write(writew, "w", unsigned short, "r", :"memory")
                     ^
   arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
    static inline void name(type val, volatile void __iomem *addr) \
                       ^~~~
   arch/x86/include/asm/io.h:66:18: error: static declaration of 'writew' follows non-static declaration
    build_mmio_write(writew, "w", unsigned short, "r", :"memory")
                     ^
   arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
    static inline void name(type val, volatile void __iomem *addr) \
                       ^~~~
   In file included from drivers/gpu/drm/i915/intel_guc.h:28:0,
                    from drivers/gpu/drm/i915/intel_guc.c:25:
   drivers/gpu/drm/i915/intel_uncore.h:230:2: note: previous implicit declaration of 'writew' was here
     write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
     ^
   drivers/gpu/drm/i915/intel_uncore.h:238:1: note: in expansion of macro '__raw_write'
    __raw_write(16, w)
    ^~~~~~~~~~~
   In file included from include/linux/io.h:25:0,
                    from include/linux/io-mapping.h:24,
                    from drivers/gpu/drm/i915/i915_vma.h:28,
                    from drivers/gpu/drm/i915/intel_guc.h:36,
                    from drivers/gpu/drm/i915/intel_guc.c:25:
   arch/x86/include/asm/io.h:67:18: warning: conflicting types for 'writel'
    build_mmio_write(writel, "l", unsigned int, "r", :"memory")
                     ^
   arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
    static inline void name(type val, volatile void __iomem *addr) \
                       ^~~~
   arch/x86/include/asm/io.h:67:18: error: static declaration of 'writel' follows non-static declaration
    build_mmio_write(writel, "l", unsigned int, "r", :"memory")
                     ^
   arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
    static inline void name(type val, volatile void __iomem *addr) \
                       ^~~~
   In file included from drivers/gpu/drm/i915/intel_guc.h:28:0,
                    from drivers/gpu/drm/i915/intel_guc.c:25:
   drivers/gpu/drm/i915/intel_uncore.h:230:2: note: previous implicit declaration of 'writel' was here
     write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
     ^
   drivers/gpu/drm/i915/intel_uncore.h:239:1: note: in expansion of macro '__raw_write'
    __raw_write(32, l)
    ^~~~~~~~~~~
   In file included from include/linux/io.h:25:0,
                    from include/linux/io-mapping.h:24,
                    from drivers/gpu/drm/i915/i915_vma.h:28,
                    from drivers/gpu/drm/i915/intel_guc.h:36,
                    from drivers/gpu/drm/i915/intel_guc.c:25:
>> arch/x86/include/asm/io.h:97:17: error: conflicting types for 'readq'
    build_mmio_read(readq, "q", u64, "=r", :"memory")
                    ^
   arch/x86/include/asm/io.h:48:20: note: in definition of macro 'build_mmio_read'
    static inline type name(const volatile void __iomem *addr) \
                       ^~~~
   In file included from drivers/gpu/drm/i915/intel_guc.h:28:0,
                    from drivers/gpu/drm/i915/intel_guc.c:25:
   drivers/gpu/drm/i915/intel_uncore.h:223:9: note: previous implicit declaration of 'readq' was here
     return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
            ^
   drivers/gpu/drm/i915/intel_uncore.h:235:1: note: in expansion of macro '__raw_read'
    __raw_read(64, q)
    ^~~~~~~~~~
   In file included from include/linux/io.h:25:0,
                    from include/linux/io-mapping.h:24,
                    from drivers/gpu/drm/i915/i915_vma.h:28,
                    from drivers/gpu/drm/i915/intel_guc.h:36,
                    from drivers/gpu/drm/i915/intel_guc.c:25:
>> arch/x86/include/asm/io.h:99:18: warning: conflicting types for 'writeq'
    build_mmio_write(writeq, "q", u64, "r", :"memory")
                     ^
   arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
    static inline void name(type val, volatile void __iomem *addr) \
                       ^~~~
>> arch/x86/include/asm/io.h:99:18: error: static declaration of 'writeq' follows non-static declaration
    build_mmio_write(writeq, "q", u64, "r", :"memory")
                     ^
   arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
    static inline void name(type val, volatile void __iomem *addr) \
                       ^~~~
   In file included from drivers/gpu/drm/i915/intel_guc.h:28:0,
                    from drivers/gpu/drm/i915/intel_guc.c:25:
   drivers/gpu/drm/i915/intel_uncore.h:230:2: note: previous implicit declaration of 'writeq' was here
     write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
     ^
   drivers/gpu/drm/i915/intel_uncore.h:240:1: note: in expansion of macro '__raw_write'
    __raw_write(64, q)
    ^~~~~~~~~~~
   cc1: some warnings being treated as errors
--
                    ^
   arch/x86/include/asm/io.h:48:20: note: in definition of macro 'build_mmio_read'
    static inline type name(const volatile void __iomem *addr) \
                       ^~~~
   In file included from drivers/gpu//drm/i915/intel_guc.h:28:0,
                    from drivers/gpu//drm/i915/intel_uc.h:27,
                    from drivers/gpu//drm/i915/intel_uc.c:25:
   drivers/gpu//drm/i915/intel_uncore.h:223:9: note: previous implicit declaration of 'readl' was here
     return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
            ^
   drivers/gpu//drm/i915/intel_uncore.h:234:1: note: in expansion of macro '__raw_read'
    __raw_read(32, l)
    ^~~~~~~~~~
   In file included from include/linux/io.h:25:0,
                    from include/linux/io-mapping.h:24,
                    from drivers/gpu//drm/i915/i915_vma.h:28,
                    from drivers/gpu//drm/i915/intel_guc.h:36,
                    from drivers/gpu//drm/i915/intel_uc.h:27,
                    from drivers/gpu//drm/i915/intel_uc.c:25:
   arch/x86/include/asm/io.h:65:18: warning: conflicting types for 'writeb'
    build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
                     ^
   arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
    static inline void name(type val, volatile void __iomem *addr) \
                       ^~~~
   arch/x86/include/asm/io.h:65:18: error: static declaration of 'writeb' follows non-static declaration
    build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
                     ^
   arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
    static inline void name(type val, volatile void __iomem *addr) \
                       ^~~~
   In file included from drivers/gpu//drm/i915/intel_guc.h:28:0,
                    from drivers/gpu//drm/i915/intel_uc.h:27,
                    from drivers/gpu//drm/i915/intel_uc.c:25:
   drivers/gpu//drm/i915/intel_uncore.h:230:2: note: previous implicit declaration of 'writeb' was here
     write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
     ^
   drivers/gpu//drm/i915/intel_uncore.h:237:1: note: in expansion of macro '__raw_write'
    __raw_write(8, b)
    ^~~~~~~~~~~
   In file included from include/linux/io.h:25:0,
                    from include/linux/io-mapping.h:24,
                    from drivers/gpu//drm/i915/i915_vma.h:28,
                    from drivers/gpu//drm/i915/intel_guc.h:36,
                    from drivers/gpu//drm/i915/intel_uc.h:27,
                    from drivers/gpu//drm/i915/intel_uc.c:25:
   arch/x86/include/asm/io.h:66:18: warning: conflicting types for 'writew'
    build_mmio_write(writew, "w", unsigned short, "r", :"memory")
                     ^
   arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
    static inline void name(type val, volatile void __iomem *addr) \
                       ^~~~
   arch/x86/include/asm/io.h:66:18: error: static declaration of 'writew' follows non-static declaration
    build_mmio_write(writew, "w", unsigned short, "r", :"memory")
                     ^
   arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
    static inline void name(type val, volatile void __iomem *addr) \
                       ^~~~
   In file included from drivers/gpu//drm/i915/intel_guc.h:28:0,
                    from drivers/gpu//drm/i915/intel_uc.h:27,
                    from drivers/gpu//drm/i915/intel_uc.c:25:
   drivers/gpu//drm/i915/intel_uncore.h:230:2: note: previous implicit declaration of 'writew' was here
     write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
     ^
   drivers/gpu//drm/i915/intel_uncore.h:238:1: note: in expansion of macro '__raw_write'
    __raw_write(16, w)
    ^~~~~~~~~~~
   In file included from include/linux/io.h:25:0,
                    from include/linux/io-mapping.h:24,
                    from drivers/gpu//drm/i915/i915_vma.h:28,
                    from drivers/gpu//drm/i915/intel_guc.h:36,
                    from drivers/gpu//drm/i915/intel_uc.h:27,
                    from drivers/gpu//drm/i915/intel_uc.c:25:
   arch/x86/include/asm/io.h:67:18: warning: conflicting types for 'writel'
    build_mmio_write(writel, "l", unsigned int, "r", :"memory")
                     ^
   arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
    static inline void name(type val, volatile void __iomem *addr) \
                       ^~~~
   arch/x86/include/asm/io.h:67:18: error: static declaration of 'writel' follows non-static declaration
    build_mmio_write(writel, "l", unsigned int, "r", :"memory")
                     ^
   arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
    static inline void name(type val, volatile void __iomem *addr) \
                       ^~~~
   In file included from drivers/gpu//drm/i915/intel_guc.h:28:0,
                    from drivers/gpu//drm/i915/intel_uc.h:27,
                    from drivers/gpu//drm/i915/intel_uc.c:25:
   drivers/gpu//drm/i915/intel_uncore.h:230:2: note: previous implicit declaration of 'writel' was here
     write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
     ^
   drivers/gpu//drm/i915/intel_uncore.h:239:1: note: in expansion of macro '__raw_write'
    __raw_write(32, l)
    ^~~~~~~~~~~
   In file included from include/linux/io.h:25:0,
                    from include/linux/io-mapping.h:24,
                    from drivers/gpu//drm/i915/i915_vma.h:28,
                    from drivers/gpu//drm/i915/intel_guc.h:36,
                    from drivers/gpu//drm/i915/intel_uc.h:27,
                    from drivers/gpu//drm/i915/intel_uc.c:25:
>> arch/x86/include/asm/io.h:97:17: error: conflicting types for 'readq'
    build_mmio_read(readq, "q", u64, "=r", :"memory")
                    ^
   arch/x86/include/asm/io.h:48:20: note: in definition of macro 'build_mmio_read'
    static inline type name(const volatile void __iomem *addr) \
                       ^~~~
   In file included from drivers/gpu//drm/i915/intel_guc.h:28:0,
                    from drivers/gpu//drm/i915/intel_uc.h:27,
                    from drivers/gpu//drm/i915/intel_uc.c:25:
   drivers/gpu//drm/i915/intel_uncore.h:223:9: note: previous implicit declaration of 'readq' was here
     return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
            ^
   drivers/gpu//drm/i915/intel_uncore.h:235:1: note: in expansion of macro '__raw_read'
    __raw_read(64, q)
    ^~~~~~~~~~
   In file included from include/linux/io.h:25:0,
                    from include/linux/io-mapping.h:24,
                    from drivers/gpu//drm/i915/i915_vma.h:28,
                    from drivers/gpu//drm/i915/intel_guc.h:36,
                    from drivers/gpu//drm/i915/intel_uc.h:27,
                    from drivers/gpu//drm/i915/intel_uc.c:25:
>> arch/x86/include/asm/io.h:99:18: warning: conflicting types for 'writeq'
    build_mmio_write(writeq, "q", u64, "r", :"memory")
                     ^
   arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
    static inline void name(type val, volatile void __iomem *addr) \
                       ^~~~
>> arch/x86/include/asm/io.h:99:18: error: static declaration of 'writeq' follows non-static declaration
    build_mmio_write(writeq, "q", u64, "r", :"memory")
                     ^
   arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
    static inline void name(type val, volatile void __iomem *addr) \
                       ^~~~
   In file included from drivers/gpu//drm/i915/intel_guc.h:28:0,
                    from drivers/gpu//drm/i915/intel_uc.h:27,
                    from drivers/gpu//drm/i915/intel_uc.c:25:
   drivers/gpu//drm/i915/intel_uncore.h:230:2: note: previous implicit declaration of 'writeq' was here
     write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
     ^
   drivers/gpu//drm/i915/intel_uncore.h:240:1: note: in expansion of macro '__raw_write'
    __raw_write(64, q)
    ^~~~~~~~~~~
   cc1: some warnings being treated as errors

vim +/readq +97 arch/x86/include/asm/io.h

93093d099 arch/x86/include/asm/io.h Ingo Molnar     2008-11-30   96  
6469a0ee0 arch/x86/include/asm/io.h Andy Shevchenko 2018-05-15  @97  build_mmio_read(readq, "q", u64, "=r", :"memory")
6469a0ee0 arch/x86/include/asm/io.h Andy Shevchenko 2018-05-15   98  build_mmio_read(__readq, "q", u64, "=r", )
6469a0ee0 arch/x86/include/asm/io.h Andy Shevchenko 2018-05-15  @99  build_mmio_write(writeq, "q", u64, "r", :"memory")
6469a0ee0 arch/x86/include/asm/io.h Andy Shevchenko 2018-05-15  100  build_mmio_write(__writeq, "q", u64, "r", )
c1f64a580 include/asm-x86/io.h      Linus Torvalds  2008-05-27  101  

:::::: The code at line 97 was first introduced by commit
:::::: 6469a0ee0a06b2ea1f5afbb1d5a3feed017d4c7a x86/io: Define readq()/writeq() to use 64-bit type

:::::: TO: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
:::::: CC: Ingo Molnar <mingo@kernel.org>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

kernel test robot March 26, 2019, 4:37 a.m. UTC | #4

Hi Daniele,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20190325]
[cannot apply to v5.1-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Daniele-Ceraolo-Spurio/more-uncore-rework/20190326-110805
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x011-201912 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All error/warnings (new ones prefixed by >>):

   In file included from drivers/gpu/drm/i915/intel_guc.h:28:0,
                    from drivers/gpu/drm/i915/intel_guc.c:25:
   drivers/gpu/drm/i915/intel_uncore.h: In function '__raw_uncore_read64':
>> drivers/gpu/drm/i915/intel_uncore.h:223:9: error: implicit declaration of function 'readq'; did you mean 'readl'? [-Werror=implicit-function-declaration]
     return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
            ^
>> drivers/gpu/drm/i915/intel_uncore.h:235:1: note: in expansion of macro '__raw_read'
    __raw_read(64, q)
    ^~~~~~~~~~
   drivers/gpu/drm/i915/intel_uncore.h: In function '__raw_uncore_write64':
>> drivers/gpu/drm/i915/intel_uncore.h:230:2: error: implicit declaration of function 'writeq'; did you mean 'writel'? [-Werror=implicit-function-declaration]
     write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
     ^
>> drivers/gpu/drm/i915/intel_uncore.h:240:1: note: in expansion of macro '__raw_write'
    __raw_write(64, q)
    ^~~~~~~~~~~
   cc1: some warnings being treated as errors

vim +223 drivers/gpu/drm/i915/intel_uncore.h

   217	
   218	/* register access functions */
   219	#define __raw_read(x__, s__) \
   220	static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
   221						    i915_reg_t reg) \
   222	{ \
 > 223		return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
   224	}
   225	
   226	#define __raw_write(x__, s__) \
   227	static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
   228						   i915_reg_t reg, u##x__ val) \
   229	{ \
 > 230		write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
   231	}
   232	__raw_read(8, b)
   233	__raw_read(16, w)
   234	__raw_read(32, l)
 > 235	__raw_read(64, q)
   236	
   237	__raw_write(8, b)
   238	__raw_write(16, w)
   239	__raw_write(32, l)
 > 240	__raw_write(64, q)
   241	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4e30f7b19b51..558d40f07ffe 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3507,32 +3507,6 @@  static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
 #define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
 #define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)
 
-#define __raw_read(x, s) \
-static inline uint##x##_t __raw_i915_read##x(const struct intel_uncore *uncore, \
-					     i915_reg_t reg) \
-{ \
-	return read##s(uncore->regs + i915_mmio_reg_offset(reg)); \
-}
-
-#define __raw_write(x, s) \
-static inline void __raw_i915_write##x(const struct intel_uncore *uncore, \
-				       i915_reg_t reg, uint##x##_t val) \
-{ \
-	write##s(val, uncore->regs + i915_mmio_reg_offset(reg)); \
-}
-__raw_read(8, b)
-__raw_read(16, w)
-__raw_read(32, l)
-__raw_read(64, q)
-
-__raw_write(8, b)
-__raw_write(16, w)
-__raw_write(32, l)
-__raw_write(64, q)
-
-#undef __raw_read
-#undef __raw_write
-
 /* These are untraced mmio-accessors that are only valid to be used inside
  * critical sections, such as inside IRQ handlers, where forcewake is explicitly
  * controlled.
@@ -3559,9 +3533,9 @@  __raw_write(64, q)
  * therefore generally be serialised, by either the dev_priv->uncore.lock or
  * a more localised lock guarding all access to that bank of registers.
  */
-#define I915_READ_FW(reg__) __raw_i915_read32(&dev_priv->uncore, (reg__))
-#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(&dev_priv->uncore, (reg__), (val__))
-#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(&dev_priv->uncore, (reg__), (val__))
+#define I915_READ_FW(reg__) __raw_uncore_read32(&dev_priv->uncore, (reg__))
+#define I915_WRITE_FW(reg__, val__) __raw_uncore_write32(&dev_priv->uncore, (reg__), (val__))
+#define I915_WRITE64_FW(reg__, val__) __raw_uncore_write64(&dev_priv->uncore, (reg__), (val__))
 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
 
 /* "Broadcast RGB" property */
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 3d0b493e4200..94d3992b599d 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -66,17 +66,17 @@  void i915_check_vgpu(struct drm_i915_private *dev_priv)
 
 	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
 
-	magic = __raw_i915_read64(uncore, vgtif_reg(magic));
+	magic = __raw_uncore_read64(uncore, vgtif_reg(magic));
 	if (magic != VGT_MAGIC)
 		return;
 
-	version_major = __raw_i915_read16(uncore, vgtif_reg(version_major));
+	version_major = __raw_uncore_read16(uncore, vgtif_reg(version_major));
 	if (version_major < VGT_VERSION_MAJOR) {
 		DRM_INFO("VGT interface version mismatch!\n");
 		return;
 	}
 
-	dev_priv->vgpu.caps = __raw_i915_read32(uncore, vgtif_reg(vgt_caps));
+	dev_priv->vgpu.caps = __raw_uncore_read32(uncore, vgtif_reg(vgt_caps));
 
 	dev_priv->vgpu.active = true;
 	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 1816eeae3ba9..3f74889c4212 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -31,7 +31,7 @@ 
 #define FORCEWAKE_ACK_TIMEOUT_MS 50
 #define GT_FIFO_TIMEOUT_MS	 10
 
-#define __raw_posting_read(uncore__, reg__) (void)__raw_i915_read32((uncore__), (reg__))
+#define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
 
 static const char * const forcewake_domain_names[] = {
 	"render",
@@ -279,7 +279,7 @@  static inline u32 gt_thread_status(struct intel_uncore *uncore)
 {
 	u32 val;
 
-	val = __raw_i915_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
+	val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
 	val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
 
 	return val;
@@ -306,7 +306,7 @@  static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
 
 static inline u32 fifo_free_entries(struct intel_uncore *uncore)
 {
-	u32 count = __raw_i915_read32(uncore, GTFIFOCTL);
+	u32 count = __raw_uncore_read32(uncore, GTFIFOCTL);
 
 	return count & GT_FIFO_FREE_ENTRIES_MASK;
 }
@@ -451,7 +451,7 @@  static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
 	if (IS_HASWELL(dev_priv) ||
 	    IS_BROADWELL(dev_priv) ||
 	    INTEL_GEN(dev_priv) >= 9) {
-		dev_priv->edram_cap = __raw_i915_read32(&dev_priv->uncore,
+		dev_priv->edram_cap = __raw_uncore_read32(&dev_priv->uncore,
 							HSW_EDRAM_CAP);
 
 		/* NB: We can't write IDICR yet because we do not have gt funcs
@@ -470,11 +470,11 @@  fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
 {
 	u32 dbg;
 
-	dbg = __raw_i915_read32(uncore, FPGA_DBG);
+	dbg = __raw_uncore_read32(uncore, FPGA_DBG);
 	if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
 		return false;
 
-	__raw_i915_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
+	__raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 
 	return true;
 }
@@ -484,11 +484,11 @@  vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
 {
 	u32 cer;
 
-	cer = __raw_i915_read32(uncore, CLAIM_ER);
+	cer = __raw_uncore_read32(uncore, CLAIM_ER);
 	if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
 		return false;
 
-	__raw_i915_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
+	__raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
 
 	return true;
 }
@@ -498,11 +498,11 @@  gen6_check_for_fifo_debug(struct intel_uncore *uncore)
 {
 	u32 fifodbg;
 
-	fifodbg = __raw_i915_read32(uncore, GTFIFODBG);
+	fifodbg = __raw_uncore_read32(uncore, GTFIFODBG);
 
 	if (unlikely(fifodbg)) {
 		DRM_DEBUG_DRIVER("GTFIFODBG = 0x08%x\n", fifodbg);
-		__raw_i915_write32(uncore, GTFIFODBG, fifodbg);
+		__raw_uncore_write32(uncore, GTFIFODBG, fifodbg);
 	}
 
 	return fifodbg;
@@ -537,10 +537,10 @@  static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
 
 	/* WaDisableShadowRegForCpd:chv */
 	if (IS_CHERRYVIEW(i915)) {
-		__raw_i915_write32(uncore, GTFIFOCTL,
-				   __raw_i915_read32(uncore, GTFIFOCTL) |
-				   GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
-				   GT_FIFO_CTL_RC6_POLICY_STALL);
+		__raw_uncore_write32(uncore, GTFIFOCTL,
+				     __raw_uncore_read32(uncore, GTFIFOCTL) |
+				     GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+				     GT_FIFO_CTL_RC6_POLICY_STALL);
 	}
 
 	iosf_mbi_punit_acquire();
@@ -1068,7 +1068,7 @@  ilk_dummy_write(struct intel_uncore *uncore)
 	/* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 	 * the chip from rc6 before touching it for real. MI_MODE is masked,
 	 * hence harmless to write 0 into. */
-	__raw_i915_write32(uncore, MI_MODE, 0);
+	__raw_uncore_write32(uncore, MI_MODE, 0);
 }
 
 static void
@@ -1110,7 +1110,7 @@  unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 static u##x \
 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 	GEN2_READ_HEADER(x); \
-	val = __raw_i915_read##x(uncore, reg); \
+	val = __raw_uncore_read##x(uncore, reg); \
 	GEN2_READ_FOOTER; \
 }
 
@@ -1119,7 +1119,7 @@  static u##x \
 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
 	GEN2_READ_HEADER(x); \
 	ilk_dummy_write(uncore); \
-	val = __raw_i915_read##x(uncore, reg); \
+	val = __raw_uncore_read##x(uncore, reg); \
 	GEN2_READ_FOOTER; \
 }
 
@@ -1189,7 +1189,7 @@  func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) {
 	fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
 	if (fw_engine) \
 		__force_wake_auto(uncore, fw_engine); \
-	val = __raw_i915_read##x(uncore, reg); \
+	val = __raw_uncore_read##x(uncore, reg); \
 	GEN6_READ_FOOTER; \
 }
 #define __gen6_read(x) __gen_read(gen6, x)
@@ -1226,7 +1226,7 @@  __gen6_read(64)
 static void \
 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 	GEN2_WRITE_HEADER; \
-	__raw_i915_write##x(uncore, reg, val); \
+	__raw_uncore_write##x(uncore, reg, val); \
 	GEN2_WRITE_FOOTER; \
 }
 
@@ -1235,7 +1235,7 @@  static void \
 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
 	GEN2_WRITE_HEADER; \
 	ilk_dummy_write(uncore); \
-	__raw_i915_write##x(uncore, reg, val); \
+	__raw_uncore_write##x(uncore, reg, val); \
 	GEN2_WRITE_FOOTER; \
 }
 
@@ -1271,7 +1271,7 @@  gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool
 	GEN6_WRITE_HEADER; \
 	if (NEEDS_FORCE_WAKE(offset)) \
 		__gen6_gt_wait_for_fifo(uncore); \
-	__raw_i915_write##x(uncore, reg, val); \
+	__raw_uncore_write##x(uncore, reg, val); \
 	GEN6_WRITE_FOOTER; \
 }
 
@@ -1283,7 +1283,7 @@  func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, boo
 	fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
 	if (fw_engine) \
 		__force_wake_auto(uncore, fw_engine); \
-	__raw_i915_write##x(uncore, reg, val); \
+	__raw_uncore_write##x(uncore, reg, val); \
 	GEN6_WRITE_FOOTER; \
 }
 #define __gen8_write(x) __gen_write(gen8, x)
@@ -1470,7 +1470,7 @@  static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
 		 * before the ecobus check.
 		 */
 
-		__raw_i915_write32(uncore, FORCEWAKE, 0);
+		__raw_uncore_write32(uncore, FORCEWAKE, 0);
 		__raw_posting_read(uncore, ECOBUS);
 
 		fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
@@ -1478,7 +1478,7 @@  static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
 
 		spin_lock_irq(&uncore->lock);
 		fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
-		ecobus = __raw_i915_read32(uncore, ECOBUS);
+		ecobus = __raw_uncore_read32(uncore, ECOBUS);
 		fw_domains_put(uncore, FORCEWAKE_RENDER);
 		spin_unlock_irq(&uncore->lock);
 
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index d345e5ab04a5..f7670cbc41c9 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -215,6 +215,33 @@  int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
 					    2, timeout_ms, NULL);
 }
 
+/* register access functions */
+#define __raw_read(x__, s__) \
+static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
+					    i915_reg_t reg) \
+{ \
+	return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
+}
+
+#define __raw_write(x__, s__) \
+static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
+					   i915_reg_t reg, u##x__ val) \
+{ \
+	write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
+}
+__raw_read(8, b)
+__raw_read(16, w)
+__raw_read(32, l)
+__raw_read(64, q)
+
+__raw_write(8, b)
+__raw_write(16, w)
+__raw_write(32, l)
+__raw_write(64, q)
+
+#undef __raw_read
+#undef __raw_write
+
 #define raw_reg_read(base, reg) \
 	readl(base + i915_mmio_reg_offset(reg))
 #define raw_reg_write(base, reg, value) \

[1/9] drm/i915: rename raw reg access functions

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