| Message ID | 20190305050546.23431-1-weiyi.lu@mediatek.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Mediatek MT8183 clock support | expand |
Resend clock patches from v4 based on v5.0-rc1. The whole series now is composed of a fix for PLL tuner (PATCH 1), clock common changes for both MT8183 & MT6765 (PATCH 2-3), clock support of MT8183 (PATCH 4-8) and resend a clock patch long time ago(PTACH 9). changes since v4: - refine for the fix of PLL tuner(PATCH 1). - add configurable pcw_chg_reg for MT8183 and the following IC(PATCH 7). changes sinve v3: - add fix tag. - small change of mtk_clk_mux data structure. - use of_property_for_each_string to iterate dependent subsys clock of power domain. - document critical clocks. - reduce some clock register error log. - few coding style fix. changes sinve v2: - refine for implementation consistency of mtk clk mux. - separate the onoff API into enable/disable API for mtk scpsys. - resend a patch about PLL rate changing. changes since v1: - refine for better code quality. - some minor bug fix of clock part, like incorrect control address and missing clocks. James Liao (1): clk: mediatek: Allow changing PLL rate when it is off Owen Chen (3): clk: mediatek: Disable tuner_en before change PLL rate clk: mediatek: Add new clkmux register API clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data Weiyi Lu (5): dt-bindings: ARM: Mediatek: Document bindings for MT8183 clk: mediatek: Add dt-bindings for MT8183 clocks clk: mediatek: Add flags support for mtk_gate data clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data clk: mediatek: Add MT8183 clock support .../arm/mediatek/mediatek,apmixedsys.txt | 1 + .../bindings/arm/mediatek/mediatek,audsys.txt | 1 + .../bindings/arm/mediatek/mediatek,camsys.txt | 22 + .../bindings/arm/mediatek/mediatek,imgsys.txt | 1 + .../arm/mediatek/mediatek,infracfg.txt | 1 + .../bindings/arm/mediatek/mediatek,ipu.txt | 43 + .../bindings/arm/mediatek/mediatek,mcucfg.txt | 1 + .../bindings/arm/mediatek/mediatek,mfgcfg.txt | 1 + .../bindings/arm/mediatek/mediatek,mmsys.txt | 1 + .../arm/mediatek/mediatek,topckgen.txt | 1 + .../arm/mediatek/mediatek,vdecsys.txt | 1 + .../arm/mediatek/mediatek,vencsys.txt | 1 + drivers/clk/mediatek/Kconfig | 75 + drivers/clk/mediatek/Makefile | 15 +- drivers/clk/mediatek/clk-gate.c | 5 +- drivers/clk/mediatek/clk-gate.h | 17 +- drivers/clk/mediatek/clk-mt8183-audio.c | 105 ++ drivers/clk/mediatek/clk-mt8183-cam.c | 63 + drivers/clk/mediatek/clk-mt8183-img.c | 63 + drivers/clk/mediatek/clk-mt8183-ipu0.c | 56 + drivers/clk/mediatek/clk-mt8183-ipu1.c | 56 + drivers/clk/mediatek/clk-mt8183-ipu_adl.c | 54 + drivers/clk/mediatek/clk-mt8183-ipu_conn.c | 123 ++ drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 54 + drivers/clk/mediatek/clk-mt8183-mm.c | 111 ++ drivers/clk/mediatek/clk-mt8183-vdec.c | 67 + drivers/clk/mediatek/clk-mt8183-venc.c | 59 + drivers/clk/mediatek/clk-mt8183.c | 1284 +++++++++++++++++ drivers/clk/mediatek/clk-mtk.c | 3 +- drivers/clk/mediatek/clk-mtk.h | 4 + drivers/clk/mediatek/clk-mux.c | 223 +++ drivers/clk/mediatek/clk-mux.h | 89 ++ drivers/clk/mediatek/clk-pll.c | 87 +- include/dt-bindings/clock/mt8183-clk.h | 422 ++++++ 34 files changed, 3073 insertions(+), 37 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ipu.txt create mode 100644 drivers/clk/mediatek/clk-mt8183-audio.c create mode 100644 drivers/clk/mediatek/clk-mt8183-cam.c create mode 100644 drivers/clk/mediatek/clk-mt8183-img.c create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu0.c create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu1.c create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu_adl.c create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu_conn.c create mode 100644 drivers/clk/mediatek/clk-mt8183-mfgcfg.c create mode 100644 drivers/clk/mediatek/clk-mt8183-mm.c create mode 100644 drivers/clk/mediatek/clk-mt8183-vdec.c create mode 100644 drivers/clk/mediatek/clk-mt8183-venc.c create mode 100644 drivers/clk/mediatek/clk-mt8183.c create mode 100644 drivers/clk/mediatek/clk-mux.c create mode 100644 drivers/clk/mediatek/clk-mux.h create mode 100644 include/dt-bindings/clock/mt8183-clk.h
Quoting Weiyi Lu (2019-03-04 21:05:37) > Resend clock patches from v4 based on v5.0-rc1. > Please stop sending two cover letters with the same content. Is there something different about your git-send-email workflow that's causing this? Hopefully git itself isn't doing this.
On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote: Hi Stephen, Just gentle ping. Many thanks. > Resend clock patches from v4 based on v5.0-rc1. > > The whole series now is composed of > a fix for PLL tuner (PATCH 1), > clock common changes for both MT8183 & MT6765 (PATCH 2-3), > clock support of MT8183 (PATCH 4-8) and > resend a clock patch long time ago(PTACH 9). > > changes since v4: > - refine for the fix of PLL tuner(PATCH 1). > - add configurable pcw_chg_reg for MT8183 and the following IC(PATCH 7). > > changes sinve v3: > - add fix tag. > - small change of mtk_clk_mux data structure. > - use of_property_for_each_string to iterate dependent subsys clock of power domain. > - document critical clocks. > - reduce some clock register error log. > - few coding style fix. > > changes sinve v2: > - refine for implementation consistency of mtk clk mux. > - separate the onoff API into enable/disable API for mtk scpsys. > - resend a patch about PLL rate changing. > > changes since v1: > - refine for better code quality. > - some minor bug fix of clock part, like incorrect control address > and missing clocks. > >