| Message ID | 20190408074147.26797-4-miquel.raynal@bootlin.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/4] dt-bindings: mtd: sunxi: Add new compatible | expand |
On Mon, Apr 08, 2019 at 09:41:47AM +0200, Miquel Raynal wrote: > In the current state, A33 NAND controllers use PIO during > transfers. Throughput can be increased thanks to the use of DMA > (mostly during reads, because of the ECC pipelining feature). > > Besides the usual addition of DMA DT properties, because the A33 > NAND DMA handling is different than for older SoCs, we must also > update the compatible which has recently been introduced for this > purpose. > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Applied, thanks! The rest is Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
On Mon, Apr 08, 2019 at 10:40:15AM +0200, Maxime Ripard wrote: > On Mon, Apr 08, 2019 at 09:41:47AM +0200, Miquel Raynal wrote: > > In the current state, A33 NAND controllers use PIO during > > transfers. Throughput can be increased thanks to the use of DMA > > (mostly during reads, because of the ECC pipelining feature). > > > > Besides the usual addition of DMA DT properties, because the A33 > > NAND DMA handling is different than for older SoCs, we must also > > update the compatible which has recently been introduced for this > > purpose. > > > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > > Applied, thanks! > > The rest is > Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Actually, the A23 was introduced before the A33, so we want to use that in the compatible. I've updated the patch while applying it, you might want to do the same. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 14a7d0288b45..f928b4bceb22 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -162,11 +162,13 @@ }; nfc: nand@1c03000 { - compatible = "allwinner,sun4i-a10-nand"; + compatible = "allwinner,sun8i-a33-nand-controller"; reg = <0x01c03000 0x1000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; clock-names = "ahb", "mod"; + dmas = <&dma 5>; + dma-names = "rxtx"; resets = <&ccu RST_BUS_NAND>; reset-names = "ahb"; pinctrl-names = "default";
In the current state, A33 NAND controllers use PIO during transfers. Throughput can be increased thanks to the use of DMA (mostly during reads, because of the ECC pipelining feature). Besides the usual addition of DMA DT properties, because the A33 NAND DMA handling is different than for older SoCs, we must also update the compatible which has recently been introduced for this purpose. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- Changes in v2: * Use 'A33' in the commit log instead of sun8i. arch/arm/boot/dts/sun8i-a23-a33.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)