| Message ID | 20190409003729.20857-4-paulo.r.zanoni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | IRQ initialization debloat and conversion to uncore | expand |
On Mon, Apr 08, 2019 at 05:37:29PM -0700, Paulo Zanoni wrote: > Make them take the uncore argument from the caller instead of passing > the implicit &dev_priv->uncore directly. This will allow us to finally > pass something that's not dev_priv->uncore in the future, and gets rid > of the implicit variables in register macros. I've not been paying much attention to the uncore developments, so I'm not sure this matches what other people think we should do. But techinally these look OK to me. Patches 2 and 3 are Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> But I guess give other people a bit of time to complain before pushing :) > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 144 +++++++++++++++++++------------- > 1 file changed, 88 insertions(+), 56 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 99a6527568cf..b6361bab1086 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -166,15 +166,15 @@ static void gen2_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, > intel_uncore_posting_read16(uncore, iir); > } > > -#define GEN8_IRQ_RESET_NDX(type, which) \ > - gen3_irq_reset(&dev_priv->uncore, GEN8_##type##_IMR(which), \ > +#define GEN8_IRQ_RESET_NDX(uncore, type, which) \ > + gen3_irq_reset((uncore), GEN8_##type##_IMR(which), \ > GEN8_##type##_IIR(which), GEN8_##type##_IER(which)) > > -#define GEN3_IRQ_RESET(type) \ > - gen3_irq_reset(&dev_priv->uncore, type##IMR, type##IIR, type##IER) > +#define GEN3_IRQ_RESET(uncore, type) \ > + gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER) > > -#define GEN2_IRQ_RESET(type) \ > - gen2_irq_reset(&dev_priv->uncore, type##IMR, type##IIR, type##IER) > +#define GEN2_IRQ_RESET(uncore, type) \ > + gen2_irq_reset((uncore), type##IMR, type##IIR, type##IER) > > /* > * We should clear IMR at preinstall/uninstall, and just check at postinstall. > @@ -233,17 +233,17 @@ static void gen2_irq_init(struct intel_uncore *uncore, i915_reg_t imr, > intel_uncore_posting_read16(uncore, imr); > } > > -#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) \ > - gen3_irq_init(&dev_priv->uncore, GEN8_##type##_IMR(which), \ > +#define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \ > + gen3_irq_init((uncore), GEN8_##type##_IMR(which), \ > GEN8_##type##_IIR(which), GEN8_##type##_IER(which), \ > imr_val, ier_val) > > -#define GEN3_IRQ_INIT(type, imr_val, ier_val) \ > - gen3_irq_init(&dev_priv->uncore, type##IMR, type##IIR, type##IER, \ > +#define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \ > + gen3_irq_init((uncore), type##IMR, type##IIR, type##IER, \ > imr_val, ier_val) > > -#define GEN2_IRQ_INIT(type, imr_val, ier_val) \ > - gen2_irq_init(&dev_priv->uncore, type##IMR, type##IIR, type##IER, \ > +#define GEN2_IRQ_INIT(uncore, type, imr_val, ier_val) \ > + gen2_irq_init((uncore), type##IMR, type##IIR, type##IER, \ > imr_val, ier_val) > > static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); > @@ -3331,10 +3331,12 @@ static void i945gm_vblank_work_fini(struct drm_i915_private *dev_priv) > > static void ibx_irq_reset(struct drm_i915_private *dev_priv) > { > + struct intel_uncore *uncore = &dev_priv->uncore; > + > if (HAS_PCH_NOP(dev_priv)) > return; > > - GEN3_IRQ_RESET(SDE); > + GEN3_IRQ_RESET(uncore, SDE); > > if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) > I915_WRITE(SERR_INT, 0xffffffff); > @@ -3362,13 +3364,17 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev) > > static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv) > { > - GEN3_IRQ_RESET(GT); > + struct intel_uncore *uncore = &dev_priv->uncore; > + > + GEN3_IRQ_RESET(uncore, GT); > if (INTEL_GEN(dev_priv) >= 6) > - GEN3_IRQ_RESET(GEN6_PM); > + GEN3_IRQ_RESET(uncore, GEN6_PM); > } > > static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) > { > + struct intel_uncore *uncore = &dev_priv->uncore; > + > if (IS_CHERRYVIEW(dev_priv)) > I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); > else > @@ -3379,12 +3385,14 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) > > i9xx_pipestat_irq_reset(dev_priv); > > - GEN3_IRQ_RESET(VLV_); > + GEN3_IRQ_RESET(uncore, VLV_); > dev_priv->irq_mask = ~0u; > } > > static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) > { > + struct intel_uncore *uncore = &dev_priv->uncore; > + > u32 pipestat_mask; > u32 enable_mask; > enum pipe pipe; > @@ -3409,7 +3417,7 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) > > dev_priv->irq_mask = ~enable_mask; > > - GEN3_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask); > + GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask); > } > > /* drm_dma.h hooks > @@ -3417,8 +3425,9 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) > static void ironlake_irq_reset(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = to_i915(dev); > + struct intel_uncore *uncore = &dev_priv->uncore; > > - GEN3_IRQ_RESET(DE); > + GEN3_IRQ_RESET(uncore, DE); > if (IS_GEN(dev_priv, 7)) > I915_WRITE(GEN7_ERR_INT, 0xffffffff); > > @@ -3449,15 +3458,18 @@ static void valleyview_irq_reset(struct drm_device *dev) > > static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) > { > - GEN8_IRQ_RESET_NDX(GT, 0); > - GEN8_IRQ_RESET_NDX(GT, 1); > - GEN8_IRQ_RESET_NDX(GT, 2); > - GEN8_IRQ_RESET_NDX(GT, 3); > + struct intel_uncore *uncore = &dev_priv->uncore; > + > + GEN8_IRQ_RESET_NDX(uncore, GT, 0); > + GEN8_IRQ_RESET_NDX(uncore, GT, 1); > + GEN8_IRQ_RESET_NDX(uncore, GT, 2); > + GEN8_IRQ_RESET_NDX(uncore, GT, 3); > } > > static void gen8_irq_reset(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = to_i915(dev); > + struct intel_uncore *uncore = &dev_priv->uncore; > int pipe; > > gen8_master_intr_disable(dev_priv->uncore.regs); > @@ -3470,11 +3482,11 @@ static void gen8_irq_reset(struct drm_device *dev) > for_each_pipe(dev_priv, pipe) > if (intel_display_power_is_enabled(dev_priv, > POWER_DOMAIN_PIPE(pipe))) > - GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); > + GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); > > - GEN3_IRQ_RESET(GEN8_DE_PORT_); > - GEN3_IRQ_RESET(GEN8_DE_MISC_); > - GEN3_IRQ_RESET(GEN8_PCU_); > + GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_); > + GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_); > + GEN3_IRQ_RESET(uncore, GEN8_PCU_); > > if (HAS_PCH_SPLIT(dev_priv)) > ibx_irq_reset(dev_priv); > @@ -3500,6 +3512,7 @@ static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv) > static void gen11_irq_reset(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > + struct intel_uncore *uncore = &dev_priv->uncore; > int pipe; > > gen11_master_intr_disable(dev_priv->uncore.regs); > @@ -3514,21 +3527,23 @@ static void gen11_irq_reset(struct drm_device *dev) > for_each_pipe(dev_priv, pipe) > if (intel_display_power_is_enabled(dev_priv, > POWER_DOMAIN_PIPE(pipe))) > - GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); > + GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); > > - GEN3_IRQ_RESET(GEN8_DE_PORT_); > - GEN3_IRQ_RESET(GEN8_DE_MISC_); > - GEN3_IRQ_RESET(GEN11_DE_HPD_); > - GEN3_IRQ_RESET(GEN11_GU_MISC_); > - GEN3_IRQ_RESET(GEN8_PCU_); > + GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_); > + GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_); > + GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_); > + GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); > + GEN3_IRQ_RESET(uncore, GEN8_PCU_); > > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) > - GEN3_IRQ_RESET(SDE); > + GEN3_IRQ_RESET(uncore, SDE); > } > > void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, > u8 pipe_mask) > { > + struct intel_uncore *uncore = &dev_priv->uncore; > + > u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; > enum pipe pipe; > > @@ -3540,7 +3555,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, > } > > for_each_pipe_masked(dev_priv, pipe, pipe_mask) > - GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, > + GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, > dev_priv->de_irq_mask[pipe], > ~dev_priv->de_irq_mask[pipe] | extra_ier); > > @@ -3550,6 +3565,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, > void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, > u8 pipe_mask) > { > + struct intel_uncore *uncore = &dev_priv->uncore; > enum pipe pipe; > > spin_lock_irq(&dev_priv->irq_lock); > @@ -3560,7 +3576,7 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, > } > > for_each_pipe_masked(dev_priv, pipe, pipe_mask) > - GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); > + GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); > > spin_unlock_irq(&dev_priv->irq_lock); > > @@ -3571,13 +3587,14 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, > static void cherryview_irq_reset(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = to_i915(dev); > + struct intel_uncore *uncore = &dev_priv->uncore; > > I915_WRITE(GEN8_MASTER_IRQ, 0); > POSTING_READ(GEN8_MASTER_IRQ); > > gen8_gt_irq_reset(dev_priv); > > - GEN3_IRQ_RESET(GEN8_PCU_); > + GEN3_IRQ_RESET(uncore, GEN8_PCU_); > > spin_lock_irq(&dev_priv->irq_lock); > if (dev_priv->display_irqs_enabled) > @@ -3862,6 +3879,7 @@ static void ibx_irq_postinstall(struct drm_device *dev) > static void gen5_gt_irq_postinstall(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = to_i915(dev); > + struct intel_uncore *uncore = &dev_priv->uncore; > u32 pm_irqs, gt_irqs; > > pm_irqs = gt_irqs = 0; > @@ -3880,7 +3898,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) > gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; > } > > - GEN3_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); > + GEN3_IRQ_INIT(uncore, GT, dev_priv->gt_irq_mask, gt_irqs); > > if (INTEL_GEN(dev_priv) >= 6) { > /* > @@ -3893,13 +3911,14 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) > } > > dev_priv->pm_imr = 0xffffffff; > - GEN3_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs); > + GEN3_IRQ_INIT(uncore, GEN6_PM, dev_priv->pm_imr, pm_irqs); > } > } > > static int ironlake_irq_postinstall(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = to_i915(dev); > + struct intel_uncore *uncore = &dev_priv->uncore; > u32 display_mask, extra_mask; > > if (INTEL_GEN(dev_priv) >= 7) { > @@ -3918,7 +3937,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) > } > > if (IS_HASWELL(dev_priv)) { > - gen3_assert_iir_is_zero(&dev_priv->uncore, EDP_PSR_IIR); > + gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR); > intel_psr_irq_control(dev_priv, dev_priv->psr.debug); > display_mask |= DE_EDP_PSR_INT_HSW; > } > @@ -3927,7 +3946,8 @@ static int ironlake_irq_postinstall(struct drm_device *dev) > > ibx_irq_pre_postinstall(dev); > > - GEN3_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); > + GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask, > + display_mask | extra_mask); > > gen5_gt_irq_postinstall(dev); > > @@ -3997,6 +4017,8 @@ static int valleyview_irq_postinstall(struct drm_device *dev) > > static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) > { > + struct intel_uncore *uncore = &dev_priv->uncore; > + > /* These are interrupts we'll toggle with the ring mask register */ > u32 gt_interrupts[] = { > (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | > @@ -4017,18 +4039,20 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) > > dev_priv->pm_ier = 0x0; > dev_priv->pm_imr = ~dev_priv->pm_ier; > - GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); > - GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); > + GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]); > + GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]); > /* > * RPS interrupts will get enabled/disabled on demand when RPS itself > * is enabled/disabled. Same wil be the case for GuC interrupts. > */ > - GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier); > - GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); > + GEN8_IRQ_INIT_NDX(uncore, GT, 2, dev_priv->pm_imr, dev_priv->pm_ier); > + GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]); > } > > static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) > { > + struct intel_uncore *uncore = &dev_priv->uncore; > + > u32 de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; > u32 de_pipe_enables; > u32 de_port_masked = GEN8_AUX_CHANNEL_A; > @@ -4064,7 +4088,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) > else if (IS_BROADWELL(dev_priv)) > de_port_enables |= GEN8_PORT_DP_A_HOTPLUG; > > - gen3_assert_iir_is_zero(&dev_priv->uncore, EDP_PSR_IIR); > + gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR); > intel_psr_irq_control(dev_priv, dev_priv->psr.debug); > > for_each_pipe(dev_priv, pipe) { > @@ -4072,20 +4096,21 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) > > if (intel_display_power_is_enabled(dev_priv, > POWER_DOMAIN_PIPE(pipe))) > - GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, > + GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, > dev_priv->de_irq_mask[pipe], > de_pipe_enables); > } > > - GEN3_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables); > - GEN3_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked); > + GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables); > + GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked); > > if (INTEL_GEN(dev_priv) >= 11) { > u32 de_hpd_masked = 0; > u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK | > GEN11_DE_TBT_HOTPLUG_MASK; > > - GEN3_IRQ_INIT(GEN11_DE_HPD_, ~de_hpd_masked, de_hpd_enables); > + GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked, > + de_hpd_enables); > gen11_hpd_detection_setup(dev_priv); > } else if (IS_GEN9_LP(dev_priv)) { > bxt_hpd_detection_setup(dev_priv); > @@ -4157,6 +4182,7 @@ static void icp_irq_postinstall(struct drm_device *dev) > static int gen11_irq_postinstall(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > + struct intel_uncore *uncore = &dev_priv->uncore; > u32 gu_misc_masked = GEN11_GU_MISC_GSE; > > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) > @@ -4165,7 +4191,7 @@ static int gen11_irq_postinstall(struct drm_device *dev) > gen11_gt_irq_postinstall(dev_priv); > gen8_de_irq_postinstall(dev_priv); > > - GEN3_IRQ_INIT(GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); > + GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); > > I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); > > @@ -4195,15 +4221,17 @@ static int cherryview_irq_postinstall(struct drm_device *dev) > static void i8xx_irq_reset(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = to_i915(dev); > + struct intel_uncore *uncore = &dev_priv->uncore; > > i9xx_pipestat_irq_reset(dev_priv); > > - GEN2_IRQ_RESET(); > + GEN2_IRQ_RESET(uncore, ); > } > > static int i8xx_irq_postinstall(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = to_i915(dev); > + struct intel_uncore *uncore = &dev_priv->uncore; > u16 enable_mask; > > I915_WRITE16(EMR, ~(I915_ERROR_PAGE_TABLE | > @@ -4221,7 +4249,7 @@ static int i8xx_irq_postinstall(struct drm_device *dev) > I915_MASTER_ERROR_INTERRUPT | > I915_USER_INTERRUPT; > > - GEN2_IRQ_INIT(, dev_priv->irq_mask, enable_mask); > + GEN2_IRQ_INIT(uncore, , dev_priv->irq_mask, enable_mask); > > /* Interrupt setup is already guaranteed to be single-threaded, this is > * just to make the assert_spin_locked check happy. */ > @@ -4357,6 +4385,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) > static void i915_irq_reset(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = to_i915(dev); > + struct intel_uncore *uncore = &dev_priv->uncore; > > if (I915_HAS_HOTPLUG(dev_priv)) { > i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); > @@ -4365,12 +4394,13 @@ static void i915_irq_reset(struct drm_device *dev) > > i9xx_pipestat_irq_reset(dev_priv); > > - GEN3_IRQ_RESET(); > + GEN3_IRQ_RESET(uncore, ); > } > > static int i915_irq_postinstall(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = to_i915(dev); > + struct intel_uncore *uncore = &dev_priv->uncore; > u32 enable_mask; > > I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | > @@ -4397,7 +4427,7 @@ static int i915_irq_postinstall(struct drm_device *dev) > dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; > } > > - GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask); > + GEN3_IRQ_INIT(uncore, , dev_priv->irq_mask, enable_mask); > > /* Interrupt setup is already guaranteed to be single-threaded, this is > * just to make the assert_spin_locked check happy. */ > @@ -4468,18 +4498,20 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) > static void i965_irq_reset(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = to_i915(dev); > + struct intel_uncore *uncore = &dev_priv->uncore; > > i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); > I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); > > i9xx_pipestat_irq_reset(dev_priv); > > - GEN3_IRQ_RESET(); > + GEN3_IRQ_RESET(uncore, ); > } > > static int i965_irq_postinstall(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = to_i915(dev); > + struct intel_uncore *uncore = &dev_priv->uncore; > u32 enable_mask; > u32 error_mask; > > @@ -4517,7 +4549,7 @@ static int i965_irq_postinstall(struct drm_device *dev) > if (IS_G4X(dev_priv)) > enable_mask |= I915_BSD_USER_INTERRUPT; > > - GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask); > + GEN3_IRQ_INIT(uncore, , dev_priv->irq_mask, enable_mask); > > /* Interrupt setup is already guaranteed to be single-threaded, this is > * just to make the assert_spin_locked check happy. */ > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 99a6527568cf..b6361bab1086 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -166,15 +166,15 @@ static void gen2_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, intel_uncore_posting_read16(uncore, iir); } -#define GEN8_IRQ_RESET_NDX(type, which) \ - gen3_irq_reset(&dev_priv->uncore, GEN8_##type##_IMR(which), \ +#define GEN8_IRQ_RESET_NDX(uncore, type, which) \ + gen3_irq_reset((uncore), GEN8_##type##_IMR(which), \ GEN8_##type##_IIR(which), GEN8_##type##_IER(which)) -#define GEN3_IRQ_RESET(type) \ - gen3_irq_reset(&dev_priv->uncore, type##IMR, type##IIR, type##IER) +#define GEN3_IRQ_RESET(uncore, type) \ + gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER) -#define GEN2_IRQ_RESET(type) \ - gen2_irq_reset(&dev_priv->uncore, type##IMR, type##IIR, type##IER) +#define GEN2_IRQ_RESET(uncore, type) \ + gen2_irq_reset((uncore), type##IMR, type##IIR, type##IER) /* * We should clear IMR at preinstall/uninstall, and just check at postinstall. @@ -233,17 +233,17 @@ static void gen2_irq_init(struct intel_uncore *uncore, i915_reg_t imr, intel_uncore_posting_read16(uncore, imr); } -#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) \ - gen3_irq_init(&dev_priv->uncore, GEN8_##type##_IMR(which), \ +#define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \ + gen3_irq_init((uncore), GEN8_##type##_IMR(which), \ GEN8_##type##_IIR(which), GEN8_##type##_IER(which), \ imr_val, ier_val) -#define GEN3_IRQ_INIT(type, imr_val, ier_val) \ - gen3_irq_init(&dev_priv->uncore, type##IMR, type##IIR, type##IER, \ +#define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \ + gen3_irq_init((uncore), type##IMR, type##IIR, type##IER, \ imr_val, ier_val) -#define GEN2_IRQ_INIT(type, imr_val, ier_val) \ - gen2_irq_init(&dev_priv->uncore, type##IMR, type##IIR, type##IER, \ +#define GEN2_IRQ_INIT(uncore, type, imr_val, ier_val) \ + gen2_irq_init((uncore), type##IMR, type##IIR, type##IER, \ imr_val, ier_val) static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); @@ -3331,10 +3331,12 @@ static void i945gm_vblank_work_fini(struct drm_i915_private *dev_priv) static void ibx_irq_reset(struct drm_i915_private *dev_priv) { + struct intel_uncore *uncore = &dev_priv->uncore; + if (HAS_PCH_NOP(dev_priv)) return; - GEN3_IRQ_RESET(SDE); + GEN3_IRQ_RESET(uncore, SDE); if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) I915_WRITE(SERR_INT, 0xffffffff); @@ -3362,13 +3364,17 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev) static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv) { - GEN3_IRQ_RESET(GT); + struct intel_uncore *uncore = &dev_priv->uncore; + + GEN3_IRQ_RESET(uncore, GT); if (INTEL_GEN(dev_priv) >= 6) - GEN3_IRQ_RESET(GEN6_PM); + GEN3_IRQ_RESET(uncore, GEN6_PM); } static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) { + struct intel_uncore *uncore = &dev_priv->uncore; + if (IS_CHERRYVIEW(dev_priv)) I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); else @@ -3379,12 +3385,14 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) i9xx_pipestat_irq_reset(dev_priv); - GEN3_IRQ_RESET(VLV_); + GEN3_IRQ_RESET(uncore, VLV_); dev_priv->irq_mask = ~0u; } static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) { + struct intel_uncore *uncore = &dev_priv->uncore; + u32 pipestat_mask; u32 enable_mask; enum pipe pipe; @@ -3409,7 +3417,7 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv->irq_mask = ~enable_mask; - GEN3_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask); + GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask); } /* drm_dma.h hooks @@ -3417,8 +3425,9 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) static void ironlake_irq_reset(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_uncore *uncore = &dev_priv->uncore; - GEN3_IRQ_RESET(DE); + GEN3_IRQ_RESET(uncore, DE); if (IS_GEN(dev_priv, 7)) I915_WRITE(GEN7_ERR_INT, 0xffffffff); @@ -3449,15 +3458,18 @@ static void valleyview_irq_reset(struct drm_device *dev) static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) { - GEN8_IRQ_RESET_NDX(GT, 0); - GEN8_IRQ_RESET_NDX(GT, 1); - GEN8_IRQ_RESET_NDX(GT, 2); - GEN8_IRQ_RESET_NDX(GT, 3); + struct intel_uncore *uncore = &dev_priv->uncore; + + GEN8_IRQ_RESET_NDX(uncore, GT, 0); + GEN8_IRQ_RESET_NDX(uncore, GT, 1); + GEN8_IRQ_RESET_NDX(uncore, GT, 2); + GEN8_IRQ_RESET_NDX(uncore, GT, 3); } static void gen8_irq_reset(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_uncore *uncore = &dev_priv->uncore; int pipe; gen8_master_intr_disable(dev_priv->uncore.regs); @@ -3470,11 +3482,11 @@ static void gen8_irq_reset(struct drm_device *dev) for_each_pipe(dev_priv, pipe) if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) - GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); + GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); - GEN3_IRQ_RESET(GEN8_DE_PORT_); - GEN3_IRQ_RESET(GEN8_DE_MISC_); - GEN3_IRQ_RESET(GEN8_PCU_); + GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_); + GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_); + GEN3_IRQ_RESET(uncore, GEN8_PCU_); if (HAS_PCH_SPLIT(dev_priv)) ibx_irq_reset(dev_priv); @@ -3500,6 +3512,7 @@ static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv) static void gen11_irq_reset(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_uncore *uncore = &dev_priv->uncore; int pipe; gen11_master_intr_disable(dev_priv->uncore.regs); @@ -3514,21 +3527,23 @@ static void gen11_irq_reset(struct drm_device *dev) for_each_pipe(dev_priv, pipe) if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) - GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); + GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); - GEN3_IRQ_RESET(GEN8_DE_PORT_); - GEN3_IRQ_RESET(GEN8_DE_MISC_); - GEN3_IRQ_RESET(GEN11_DE_HPD_); - GEN3_IRQ_RESET(GEN11_GU_MISC_); - GEN3_IRQ_RESET(GEN8_PCU_); + GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_); + GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_); + GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_); + GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); + GEN3_IRQ_RESET(uncore, GEN8_PCU_); if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) - GEN3_IRQ_RESET(SDE); + GEN3_IRQ_RESET(uncore, SDE); } void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, u8 pipe_mask) { + struct intel_uncore *uncore = &dev_priv->uncore; + u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; enum pipe pipe; @@ -3540,7 +3555,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, } for_each_pipe_masked(dev_priv, pipe, pipe_mask) - GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, + GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, dev_priv->de_irq_mask[pipe], ~dev_priv->de_irq_mask[pipe] | extra_ier); @@ -3550,6 +3565,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, u8 pipe_mask) { + struct intel_uncore *uncore = &dev_priv->uncore; enum pipe pipe; spin_lock_irq(&dev_priv->irq_lock); @@ -3560,7 +3576,7 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, } for_each_pipe_masked(dev_priv, pipe, pipe_mask) - GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); + GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); spin_unlock_irq(&dev_priv->irq_lock); @@ -3571,13 +3587,14 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, static void cherryview_irq_reset(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_uncore *uncore = &dev_priv->uncore; I915_WRITE(GEN8_MASTER_IRQ, 0); POSTING_READ(GEN8_MASTER_IRQ); gen8_gt_irq_reset(dev_priv); - GEN3_IRQ_RESET(GEN8_PCU_); + GEN3_IRQ_RESET(uncore, GEN8_PCU_); spin_lock_irq(&dev_priv->irq_lock); if (dev_priv->display_irqs_enabled) @@ -3862,6 +3879,7 @@ static void ibx_irq_postinstall(struct drm_device *dev) static void gen5_gt_irq_postinstall(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_uncore *uncore = &dev_priv->uncore; u32 pm_irqs, gt_irqs; pm_irqs = gt_irqs = 0; @@ -3880,7 +3898,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; } - GEN3_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); + GEN3_IRQ_INIT(uncore, GT, dev_priv->gt_irq_mask, gt_irqs); if (INTEL_GEN(dev_priv) >= 6) { /* @@ -3893,13 +3911,14 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) } dev_priv->pm_imr = 0xffffffff; - GEN3_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs); + GEN3_IRQ_INIT(uncore, GEN6_PM, dev_priv->pm_imr, pm_irqs); } } static int ironlake_irq_postinstall(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_uncore *uncore = &dev_priv->uncore; u32 display_mask, extra_mask; if (INTEL_GEN(dev_priv) >= 7) { @@ -3918,7 +3937,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) } if (IS_HASWELL(dev_priv)) { - gen3_assert_iir_is_zero(&dev_priv->uncore, EDP_PSR_IIR); + gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR); intel_psr_irq_control(dev_priv, dev_priv->psr.debug); display_mask |= DE_EDP_PSR_INT_HSW; } @@ -3927,7 +3946,8 @@ static int ironlake_irq_postinstall(struct drm_device *dev) ibx_irq_pre_postinstall(dev); - GEN3_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); + GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask, + display_mask | extra_mask); gen5_gt_irq_postinstall(dev); @@ -3997,6 +4017,8 @@ static int valleyview_irq_postinstall(struct drm_device *dev) static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) { + struct intel_uncore *uncore = &dev_priv->uncore; + /* These are interrupts we'll toggle with the ring mask register */ u32 gt_interrupts[] = { (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | @@ -4017,18 +4039,20 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv->pm_ier = 0x0; dev_priv->pm_imr = ~dev_priv->pm_ier; - GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); - GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); + GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]); + GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]); /* * RPS interrupts will get enabled/disabled on demand when RPS itself * is enabled/disabled. Same wil be the case for GuC interrupts. */ - GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier); - GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); + GEN8_IRQ_INIT_NDX(uncore, GT, 2, dev_priv->pm_imr, dev_priv->pm_ier); + GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]); } static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) { + struct intel_uncore *uncore = &dev_priv->uncore; + u32 de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; u32 de_pipe_enables; u32 de_port_masked = GEN8_AUX_CHANNEL_A; @@ -4064,7 +4088,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) else if (IS_BROADWELL(dev_priv)) de_port_enables |= GEN8_PORT_DP_A_HOTPLUG; - gen3_assert_iir_is_zero(&dev_priv->uncore, EDP_PSR_IIR); + gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR); intel_psr_irq_control(dev_priv, dev_priv->psr.debug); for_each_pipe(dev_priv, pipe) { @@ -4072,20 +4096,21 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) - GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, + GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, dev_priv->de_irq_mask[pipe], de_pipe_enables); } - GEN3_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables); - GEN3_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked); + GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables); + GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked); if (INTEL_GEN(dev_priv) >= 11) { u32 de_hpd_masked = 0; u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK; - GEN3_IRQ_INIT(GEN11_DE_HPD_, ~de_hpd_masked, de_hpd_enables); + GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked, + de_hpd_enables); gen11_hpd_detection_setup(dev_priv); } else if (IS_GEN9_LP(dev_priv)) { bxt_hpd_detection_setup(dev_priv); @@ -4157,6 +4182,7 @@ static void icp_irq_postinstall(struct drm_device *dev) static int gen11_irq_postinstall(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_uncore *uncore = &dev_priv->uncore; u32 gu_misc_masked = GEN11_GU_MISC_GSE; if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) @@ -4165,7 +4191,7 @@ static int gen11_irq_postinstall(struct drm_device *dev) gen11_gt_irq_postinstall(dev_priv); gen8_de_irq_postinstall(dev_priv); - GEN3_IRQ_INIT(GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); + GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); @@ -4195,15 +4221,17 @@ static int cherryview_irq_postinstall(struct drm_device *dev) static void i8xx_irq_reset(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_uncore *uncore = &dev_priv->uncore; i9xx_pipestat_irq_reset(dev_priv); - GEN2_IRQ_RESET(); + GEN2_IRQ_RESET(uncore, ); } static int i8xx_irq_postinstall(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_uncore *uncore = &dev_priv->uncore; u16 enable_mask; I915_WRITE16(EMR, ~(I915_ERROR_PAGE_TABLE | @@ -4221,7 +4249,7 @@ static int i8xx_irq_postinstall(struct drm_device *dev) I915_MASTER_ERROR_INTERRUPT | I915_USER_INTERRUPT; - GEN2_IRQ_INIT(, dev_priv->irq_mask, enable_mask); + GEN2_IRQ_INIT(uncore, , dev_priv->irq_mask, enable_mask); /* Interrupt setup is already guaranteed to be single-threaded, this is * just to make the assert_spin_locked check happy. */ @@ -4357,6 +4385,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) static void i915_irq_reset(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_uncore *uncore = &dev_priv->uncore; if (I915_HAS_HOTPLUG(dev_priv)) { i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); @@ -4365,12 +4394,13 @@ static void i915_irq_reset(struct drm_device *dev) i9xx_pipestat_irq_reset(dev_priv); - GEN3_IRQ_RESET(); + GEN3_IRQ_RESET(uncore, ); } static int i915_irq_postinstall(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_uncore *uncore = &dev_priv->uncore; u32 enable_mask; I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | @@ -4397,7 +4427,7 @@ static int i915_irq_postinstall(struct drm_device *dev) dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; } - GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask); + GEN3_IRQ_INIT(uncore, , dev_priv->irq_mask, enable_mask); /* Interrupt setup is already guaranteed to be single-threaded, this is * just to make the assert_spin_locked check happy. */ @@ -4468,18 +4498,20 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) static void i965_irq_reset(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_uncore *uncore = &dev_priv->uncore; i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); i9xx_pipestat_irq_reset(dev_priv); - GEN3_IRQ_RESET(); + GEN3_IRQ_RESET(uncore, ); } static int i965_irq_postinstall(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_uncore *uncore = &dev_priv->uncore; u32 enable_mask; u32 error_mask; @@ -4517,7 +4549,7 @@ static int i965_irq_postinstall(struct drm_device *dev) if (IS_G4X(dev_priv)) enable_mask |= I915_BSD_USER_INTERRUPT; - GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask); + GEN3_IRQ_INIT(uncore, , dev_priv->irq_mask, enable_mask); /* Interrupt setup is already guaranteed to be single-threaded, this is * just to make the assert_spin_locked check happy. */
Make them take the uncore argument from the caller instead of passing the implicit &dev_priv->uncore directly. This will allow us to finally pass something that's not dev_priv->uncore in the future, and gets rid of the implicit variables in register macros. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 144 +++++++++++++++++++------------- 1 file changed, 88 insertions(+), 56 deletions(-)