diff mbox series

ARM: dts: rockchip: Add BT_EN to the power sequence for veyron

Message ID 20190409231405.189335-1-mka@chromium.org (mailing list archive)
State New, archived
Headers show
Series ARM: dts: rockchip: Add BT_EN to the power sequence for veyron | expand

Commit Message

Matthias Kaehlcke April 9, 2019, 11:14 p.m. UTC
Add GPIO D5 (BT_ENABLE_L) as reset-GPIO to the power sequence for the
Bluetooth/WiFi module. On devices with a Broadcom module the signal
needs to be asserted to use Bluetooth.

Note that BT_ENABLE_L is a misnomer in the schematics, the signal
actually is active-high.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
---
 arch/arm/boot/dts/rk3288-veyron.dtsi | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

Comments

Doug Anderson April 10, 2019, 8:59 p.m. UTC | #1
Hi,

On Tue, Apr 9, 2019 at 4:14 PM Matthias Kaehlcke <mka@chromium.org> wrote:
>
> Add GPIO D5 (BT_ENABLE_L) as reset-GPIO to the power sequence for the
> Bluetooth/WiFi module. On devices with a Broadcom module the signal
> needs to be asserted to use Bluetooth.
>
> Note that BT_ENABLE_L is a misnomer in the schematics, the signal
> actually is active-high.
>
> Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
> ---
>  arch/arm/boot/dts/rk3288-veyron.dtsi | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)

Looks right to me.  Thanks!

Note that this might enable the signals in a different order than in
the downstream Chrome OS kernel, but it looks like it doesn't matter
in this case since the datasheet for the AzureWave module talks about
enabling / disabling these pins in either order.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Heiko Stübner April 11, 2019, 11:38 a.m. UTC | #2
Am Mittwoch, 10. April 2019, 01:14:05 CEST schrieb Matthias Kaehlcke:
> Add GPIO D5 (BT_ENABLE_L) as reset-GPIO to the power sequence for the
> Bluetooth/WiFi module. On devices with a Broadcom module the signal
> needs to be asserted to use Bluetooth.
> 
> Note that BT_ENABLE_L is a misnomer in the schematics, the signal
> actually is active-high.
> 
> Signed-off-by: Matthias Kaehlcke <mka@chromium.org>

applied for 5.2 with Doug's rb.

Thanks
Heiko
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index 0bc2409f6903..a4cd851dc313 100644
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -62,12 +62,19 @@ 
 		pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>;
 
 		/*
-		 * On the module itself this is one of these (depending
-		 * on the actual card populated):
+		 * Depending on the actual card populated GPIO4 D4 and D5
+		 * correspond to one of these signals on the module:
+		 *
+		 * D4:
 		 * - SDIO_RESET_L_WL_REG_ON
 		 * - PDN (power down when low)
+		 *
+		 * D5:
+		 * - BT_I2S_WS_BT_RFDISABLE_L
+		 * - No connect
 		 */
-		reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
+		reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>,
+			      <&gpio4 RK_PD5 GPIO_ACTIVE_LOW>;
 	};
 
 	vcc_5v: vcc-5v {