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[0/3] clk: keystone: sci-clk: perf improvements

Message ID 1555093342-428-1-git-send-email-t-kristo@ti.com (mailing list archive)
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Series clk: keystone: sci-clk: perf improvements | expand

Message

Tero Kristo April 12, 2019, 6:22 p.m. UTC 
Hi,

After some thinking, I decided to switch the clock scan method for
the sci-clk completely over to DT based scan. For example, on am65xx,
the boot time improvement for the clock probe is from 398ms down to
7.3ms. I retained the full firmware scan code behind a separate
Kconfig option; this can be useful for some debugging purposes if
someone needs to see all the clocks in a device.

Also, added patch #1 for cropping down the registered clock names,
currently they are pretty long forms containing the full interconnect
node paths, which makes the debugfs sort of un-usable.

-Tero

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

Comments

Tero Kristo April 17, 2019, 11:14 a.m. UTC | #1 
Hi Santosh,

Seems I missed adding you to delivery of this series, sorry about that. 
Do you want me to re-post?

-Tero

On 12/04/2019 21:22, Tero Kristo wrote:
> Hi,
> 
> After some thinking, I decided to switch the clock scan method for
> the sci-clk completely over to DT based scan. For example, on am65xx,
> the boot time improvement for the clock probe is from 398ms down to
> 7.3ms. I retained the full firmware scan code behind a separate
> Kconfig option; this can be useful for some debugging purposes if
> someone needs to see all the clocks in a device.
> 
> Also, added patch #1 for cropping down the registered clock names,
> currently they are pretty long forms containing the full interconnect
> node paths, which makes the debugfs sort of un-usable.
> 
> -Tero
> 
> --
> 

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki