| Message ID | 20190419221803.99322-2-dianders@chromium.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] ARM: errata: Workaround errata A12 857271 / A17 857272 | expand |
Hi Doug, On 19/04/2019 23:18, Douglas Anderson wrote: > This adds a code for turning on chicken bit 11, which appears to avoid > a potential CPU deadlock that could occur. The exact set of > instruction needed to trigger this errata is not totaly known but we > have a high level of confidence that the problem is fixed by setting > chicken bit 11. > > All details are in http://crbug.com/711784 > > This erratum has no known number and thus I have tagged it CR711784 > (after the Chrome OS bug number). I have created separate A12 / A17 > configs to match how the rest of the A12 / A17 errata is handled. The written-up workarounds for 85727[12] do actually say to set both bits 10 and 11 of the diagnostic register, so you could probably just fold this into the first patch and not have to worry about what to call it. Robin. > Signed-off-by: Douglas Anderson <dianders@chromium.org> > --- > > arch/arm/Kconfig | 18 ++++++++++++++++++ > arch/arm/mm/proc-v7.S | 10 ++++++++++ > 2 files changed, 28 insertions(+) > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 4376fe74f95e..34ec9039206b 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -1181,6 +1181,13 @@ config ARM_ERRATA_857271 > hang. The workaround is expected to have a negligible performance > impact. > > +config ARM_ERRATA_CR711784_A12 > + bool "ARM errata: A12: conditional instructions can lead to a CPU hang" > + depends on CPU_V7 > + help > + This option enables the workaround for a Cortex-A12 erratum without a > + number. The problems are best described in https://crbug.com/711784 > + > config ARM_ERRATA_852421 > bool "ARM errata: A17: DMB ST might fail to create order between stores" > depends on CPU_V7 > @@ -1212,6 +1219,17 @@ config ARM_ERRATA_857272 > config option from the A12 erratum due to the way errata are checked > for and handled. > > +config ARM_ERRATA_CR711784_A17 > + bool "ARM errata: A17: conditional instructions can lead to a CPU hang" > + depends on CPU_V7 > + help > + This option enables the workaround for a Cortex-A17 erratum without a > + number. The problems are best described in https://crbug.com/711784 > + This erratum is not known to be fixed in any A17 revision. > + This is identical to Cortex-A12 erratum CR711784. It is a separate > + config option from the A12 erratum due to the way errata are checked > + for and handled. > + > endmenu > > source "arch/arm/common/Kconfig" > diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S > index cd2accbab844..a5156ea734ee 100644 > --- a/arch/arm/mm/proc-v7.S > +++ b/arch/arm/mm/proc-v7.S > @@ -396,6 +396,11 @@ __ca12_errata: > mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register > orr r10, r10, #1 << 10 @ set bit #10 > mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register > +#endif > +#ifdef CONFIG_ARM_ERRATA_CR711784_A12 > + mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register > + orr r10, r10, #1 << 11 @ set bit #11 > + mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register > #endif > b __errata_finish > > @@ -416,6 +421,11 @@ __ca17_errata: > mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register > orr r10, r10, #1 << 10 @ set bit #10 > mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register > +#endif > +#ifdef CONFIG_ARM_ERRATA_CR711784_A17 > + mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register > + orr r10, r10, #1 << 11 @ set bit #11 > + mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register > #endif > b __errata_finish > >
Hi, On Tue, Apr 23, 2019 at 3:19 AM Robin Murphy <robin.murphy@arm.com> wrote: > > Hi Doug, > > On 19/04/2019 23:18, Douglas Anderson wrote: > > This adds a code for turning on chicken bit 11, which appears to avoid > > a potential CPU deadlock that could occur. The exact set of > > instruction needed to trigger this errata is not totaly known but we > > have a high level of confidence that the problem is fixed by setting > > chicken bit 11. > > > > All details are in http://crbug.com/711784 > > > > This erratum has no known number and thus I have tagged it CR711784 > > (after the Chrome OS bug number). I have created separate A12 / A17 > > configs to match how the rest of the A12 / A17 errata is handled. > > The written-up workarounds for 85727[12] do actually say to set both > bits 10 and 11 of the diagnostic register, so you could probably just > fold this into the first patch and not have to worry about what to call it. > > Robin. Thanks! I was unable to find any official docs here and my past contacts with ARM about this matter have been silent. All I had was a preliminary errata description and it only included bit 10. I'll spin a v2 with them both together then. -Doug
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4376fe74f95e..34ec9039206b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1181,6 +1181,13 @@ config ARM_ERRATA_857271 hang. The workaround is expected to have a negligible performance impact. +config ARM_ERRATA_CR711784_A12 + bool "ARM errata: A12: conditional instructions can lead to a CPU hang" + depends on CPU_V7 + help + This option enables the workaround for a Cortex-A12 erratum without a + number. The problems are best described in https://crbug.com/711784 + config ARM_ERRATA_852421 bool "ARM errata: A17: DMB ST might fail to create order between stores" depends on CPU_V7 @@ -1212,6 +1219,17 @@ config ARM_ERRATA_857272 config option from the A12 erratum due to the way errata are checked for and handled. +config ARM_ERRATA_CR711784_A17 + bool "ARM errata: A17: conditional instructions can lead to a CPU hang" + depends on CPU_V7 + help + This option enables the workaround for a Cortex-A17 erratum without a + number. The problems are best described in https://crbug.com/711784 + This erratum is not known to be fixed in any A17 revision. + This is identical to Cortex-A12 erratum CR711784. It is a separate + config option from the A12 erratum due to the way errata are checked + for and handled. + endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index cd2accbab844..a5156ea734ee 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -396,6 +396,11 @@ __ca12_errata: mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register orr r10, r10, #1 << 10 @ set bit #10 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif +#ifdef CONFIG_ARM_ERRATA_CR711784_A12 + mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register + orr r10, r10, #1 << 11 @ set bit #11 + mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register #endif b __errata_finish @@ -416,6 +421,11 @@ __ca17_errata: mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register orr r10, r10, #1 << 10 @ set bit #10 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif +#ifdef CONFIG_ARM_ERRATA_CR711784_A17 + mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register + orr r10, r10, #1 << 11 @ set bit #11 + mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register #endif b __errata_finish
This adds a code for turning on chicken bit 11, which appears to avoid a potential CPU deadlock that could occur. The exact set of instruction needed to trigger this errata is not totaly known but we have a high level of confidence that the problem is fixed by setting chicken bit 11. All details are in http://crbug.com/711784 This erratum has no known number and thus I have tagged it CR711784 (after the Chrome OS bug number). I have created separate A12 / A17 configs to match how the rest of the A12 / A17 errata is handled. Signed-off-by: Douglas Anderson <dianders@chromium.org> --- arch/arm/Kconfig | 18 ++++++++++++++++++ arch/arm/mm/proc-v7.S | 10 ++++++++++ 2 files changed, 28 insertions(+)