| Message ID | 20190410174139.20012-3-tiny.windzz@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | cpufreq: Add sunxi nvmem based CPU scaling driver | expand |
On Wed, Apr 10, 2019 at 01:41:39PM -0400, Yangtao Li wrote: > Allwinner Process Voltage Scaling Tables defines the voltage and > frequency value based on the speedbin blown in the efuse combination. > The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to > provide the OPP framework with required information. > This is used to determine the voltage and frequency value for each > OPP of operating-points-v2 table when it is parsed by the OPP framework. > > The "allwinner,cpu-operating-points-v2" DT extends the "operating-points-v2" > with following parameters: > - nvmem-cells (NVMEM area containig the speedbin information) > - opp-microvolt-<name>: voltage in micro Volts. > At runtime, the platform can pick a <name> and matching > opp-microvolt-<name> property. > HW: <name>: > sun50iw-h6 speed0 speed1 speed2 We already have at least one way to support speed bins with QC kryo binding. Why do we need a different way? > > Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> > --- > .../bindings/opp/sunxi-nvmem-cpufreq.txt | 168 ++++++++++++++++++ > 1 file changed, 168 insertions(+) > create mode 100644 Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
On Sat, Apr 27, 2019 at 5:15 AM Rob Herring <robh@kernel.org> wrote: > > On Wed, Apr 10, 2019 at 01:41:39PM -0400, Yangtao Li wrote: > > Allwinner Process Voltage Scaling Tables defines the voltage and > > frequency value based on the speedbin blown in the efuse combination. > > The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to > > provide the OPP framework with required information. > > This is used to determine the voltage and frequency value for each > > OPP of operating-points-v2 table when it is parsed by the OPP framework. > > > > The "allwinner,cpu-operating-points-v2" DT extends the "operating-points-v2" > > with following parameters: > > - nvmem-cells (NVMEM area containig the speedbin information) > > - opp-microvolt-<name>: voltage in micro Volts. > > At runtime, the platform can pick a <name> and matching > > opp-microvolt-<name> property. > > HW: <name>: > > sun50iw-h6 speed0 speed1 speed2 > > We already have at least one way to support speed bins with QC kryo > binding. Why do we need a different way? For some SOCs, for some reason (making the CPU have approximate performance), they use the same frequency but different voltage. In the case where this speed bin is not a lot and opp uses the same frequency, too many repeated opp nodes are a bit redundant and not intuitive enough. So, I think it's worth the new method. Yangtao > > > > > Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> > > --- > > .../bindings/opp/sunxi-nvmem-cpufreq.txt | 168 ++++++++++++++++++ > > 1 file changed, 168 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
On Sun, Apr 28, 2019 at 4:53 AM Frank Lee <tiny.windzz@gmail.com> wrote: > > On Sat, Apr 27, 2019 at 5:15 AM Rob Herring <robh@kernel.org> wrote: > > > > On Wed, Apr 10, 2019 at 01:41:39PM -0400, Yangtao Li wrote: > > > Allwinner Process Voltage Scaling Tables defines the voltage and > > > frequency value based on the speedbin blown in the efuse combination. > > > The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to > > > provide the OPP framework with required information. > > > This is used to determine the voltage and frequency value for each > > > OPP of operating-points-v2 table when it is parsed by the OPP framework. > > > > > > The "allwinner,cpu-operating-points-v2" DT extends the "operating-points-v2" > > > with following parameters: > > > - nvmem-cells (NVMEM area containig the speedbin information) > > > - opp-microvolt-<name>: voltage in micro Volts. > > > At runtime, the platform can pick a <name> and matching > > > opp-microvolt-<name> property. > > > HW: <name>: > > > sun50iw-h6 speed0 speed1 speed2 > > > > We already have at least one way to support speed bins with QC kryo > > binding. Why do we need a different way? > > For some SOCs, for some reason (making the CPU have approximate performance), > they use the same frequency but different voltage. In the case where > this speed bin > is not a lot and opp uses the same frequency, too many repeated opp > nodes are a bit > redundant and not intuitive enough. > > So, I think it's worth the new method. Well, I don't. We can't have every SoC vendor doing their own thing just because they want to. If there are technical reasons why existing bindings don't work, then maybe we need to do something different. But I haven't heard any reasons. Rob
On 29-04-19, 11:18, Rob Herring wrote: > On Sun, Apr 28, 2019 at 4:53 AM Frank Lee <tiny.windzz@gmail.com> wrote: > > > > On Sat, Apr 27, 2019 at 5:15 AM Rob Herring <robh@kernel.org> wrote: > > > > > > On Wed, Apr 10, 2019 at 01:41:39PM -0400, Yangtao Li wrote: > > > > Allwinner Process Voltage Scaling Tables defines the voltage and > > > > frequency value based on the speedbin blown in the efuse combination. > > > > The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to > > > > provide the OPP framework with required information. > > > > This is used to determine the voltage and frequency value for each > > > > OPP of operating-points-v2 table when it is parsed by the OPP framework. > > > > > > > > The "allwinner,cpu-operating-points-v2" DT extends the "operating-points-v2" > > > > with following parameters: > > > > - nvmem-cells (NVMEM area containig the speedbin information) > > > > - opp-microvolt-<name>: voltage in micro Volts. > > > > At runtime, the platform can pick a <name> and matching > > > > opp-microvolt-<name> property. > > > > HW: <name>: > > > > sun50iw-h6 speed0 speed1 speed2 > > > > > > We already have at least one way to support speed bins with QC kryo > > > binding. Why do we need a different way? > > > > For some SOCs, for some reason (making the CPU have approximate performance), > > they use the same frequency but different voltage. In the case where > > this speed bin > > is not a lot and opp uses the same frequency, too many repeated opp > > nodes are a bit > > redundant and not intuitive enough. > > > > So, I think it's worth the new method. > > Well, I don't. > > We can't have every SoC vendor doing their own thing just because they > want to. If there are technical reasons why existing bindings don't > work, then maybe we need to do something different. But I haven't > heard any reasons. Well there is a good reason for attempting the new bindings and I wasn't sure if updating the earlier bindings or adding another one for platform is correct. As we aren't really adding new bindings, but just documentation around it. So there are two ways OPP core support this thing: - opp-supported-hw: This is a better fit if we have a smaller group of frequencies to select from a bigger group, so we disable non-required OPPs completely. This is what Qcom did as they wanted to select different frequencies all together. - opp-microvolt-<name>: This is a better fit if the frequencies remain same and only few of the properties like voltage/current have a different value. So we don't disable any OPPs but just select the right voltage/current for those frequencies. This avoids unnecessary duplication of the OPPs in DT and that's what allwinner guys want. The kryo nvmem bindings currently supports opp-supported-hw, maybe we can add mention support for second one in the same file and rename it well.
On Tue, Apr 30, 2019 at 12:42 PM Viresh Kumar <viresh.kumar@linaro.org> wrote: > > On 29-04-19, 11:18, Rob Herring wrote: > > On Sun, Apr 28, 2019 at 4:53 AM Frank Lee <tiny.windzz@gmail.com> wrote: > > > > > > On Sat, Apr 27, 2019 at 5:15 AM Rob Herring <robh@kernel.org> wrote: > > > > > > > > On Wed, Apr 10, 2019 at 01:41:39PM -0400, Yangtao Li wrote: > > > > > Allwinner Process Voltage Scaling Tables defines the voltage and > > > > > frequency value based on the speedbin blown in the efuse combination. > > > > > The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to > > > > > provide the OPP framework with required information. > > > > > This is used to determine the voltage and frequency value for each > > > > > OPP of operating-points-v2 table when it is parsed by the OPP framework. > > > > > > > > > > The "allwinner,cpu-operating-points-v2" DT extends the "operating-points-v2" > > > > > with following parameters: > > > > > - nvmem-cells (NVMEM area containig the speedbin information) > > > > > - opp-microvolt-<name>: voltage in micro Volts. > > > > > At runtime, the platform can pick a <name> and matching > > > > > opp-microvolt-<name> property. > > > > > HW: <name>: > > > > > sun50iw-h6 speed0 speed1 speed2 > > > > > > > > We already have at least one way to support speed bins with QC kryo > > > > binding. Why do we need a different way? > > > > > > For some SOCs, for some reason (making the CPU have approximate performance), > > > they use the same frequency but different voltage. In the case where > > > this speed bin > > > is not a lot and opp uses the same frequency, too many repeated opp > > > nodes are a bit > > > redundant and not intuitive enough. > > > > > > So, I think it's worth the new method. > > > > Well, I don't. > > > > We can't have every SoC vendor doing their own thing just because they > > want to. If there are technical reasons why existing bindings don't > > work, then maybe we need to do something different. But I haven't > > heard any reasons. > > Well there is a good reason for attempting the new bindings and I wasn't sure if > updating the earlier bindings or adding another one for platform is correct. As > we aren't really adding new bindings, but just documentation around it. We didn't really add anything else, it still revolves around the features that opp already supports. > > So there are two ways OPP core support this thing: > > - opp-supported-hw: This is a better fit if we have a smaller group of > frequencies to select from a bigger group, so we disable non-required OPPs > completely. This is what Qcom did as they wanted to select different > frequencies all together. > > - opp-microvolt-<name>: This is a better fit if the frequencies remain same and > only few of the properties like voltage/current have a different value. So we > don't disable any OPPs but just select the right voltage/current for those > frequencies. This avoids unnecessary duplication of the OPPs in DT and that's > what allwinner guys want. > > The kryo nvmem bindings currently supports opp-supported-hw, maybe we can add > mention support for second one in the same file and rename it well. So which way is correct? Thx, Yangtao > > -- > viresh
Hi Rob, PING...
diff --git a/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt new file mode 100644 index 000000000000..9a1826724b47 --- /dev/null +++ b/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt @@ -0,0 +1,168 @@ +Allwinner Technologies, Inc. NVMEM CPUFreq and OPP bindings +=================================== + +For some SoCs, the CPU frequency subset and voltage value of each OPP +varies based on the silicon variant in use. Allwinner Process Voltage +Scaling Tables defines the voltage and frequency value based on the +speedbin blown in the efuse combination. The sunxi-cpufreq-nvmem driver +reads the efuse value from the SoC to provide the OPP framework with +required information. + +Required properties: +-------------------- +In 'cpus' nodes: +- operating-points-v2: Phandle to the operating-points-v2 table to use. + +In 'operating-points-v2' table: +- compatible: Should be + - 'allwinner,cpu-operating-points-v2'. +- nvmem-cells: A phandle pointing to a nvmem-cells node representing the + efuse registers that has information about the + speedbin that is used to select the right frequency/voltage + value pair. + Please refer the for nvmem-cells + bindings Documentation/devicetree/bindings/nvmem/nvmem.txt + and also examples below. + +In every OPP node: +- opp-microvolt-<name>: Voltage in micro Volts. + At runtime, the platform can pick a <name> and + matching opp-microvolt-<name> property. + [See: opp.txt] + HW: <name>: + sun50iw-h6 speed0 speed1 speed2 + +Example 1: +--------- + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <2>; + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <3>; + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; + }; + }; + + cpu_opp_table: opp_table { + compatible = "operating-points-v2-sunxi-cpu"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + opp@480000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <480000000>; + + opp-microvolt-speed0 = <880000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <800000>; + }; + + opp@720000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <720000000>; + + opp-microvolt-speed0 = <880000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <800000>; + }; + + opp@816000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <816000000>; + + opp-microvolt-speed0 = <880000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <800000>; + }; + + opp@888000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <888000000>; + + opp-microvolt-speed0 = <940000>; + opp-microvolt-speed1 = <820000>; + opp-microvolt-speed2 = <800000>; + }; + + opp@1080000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1080000000>; + + opp-microvolt-speed0 = <1060000>; + opp-microvolt-speed1 = <880000>; + opp-microvolt-speed2 = <840000>; + }; + + opp@1320000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1320000000>; + + opp-microvolt-speed0 = <1160000>; + opp-microvolt-speed1 = <940000>; + opp-microvolt-speed2 = <900000>; + }; + + opp@1488000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1488000000>; + + opp-microvolt-speed0 = <1160000>; + opp-microvolt-speed1 = <1000000>; + opp-microvolt-speed2 = <960000>; + }; + }; +.... +soc { +.... + sid: sid@3006000 { + compatible = "allwinner,sun50i-h6-sid"; + reg = <0x03006000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + .... + speedbin_efuse: speed@1c { + reg = <0x1c 4>; + }; + }; +};
Allwinner Process Voltage Scaling Tables defines the voltage and frequency value based on the speedbin blown in the efuse combination. The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to provide the OPP framework with required information. This is used to determine the voltage and frequency value for each OPP of operating-points-v2 table when it is parsed by the OPP framework. The "allwinner,cpu-operating-points-v2" DT extends the "operating-points-v2" with following parameters: - nvmem-cells (NVMEM area containig the speedbin information) - opp-microvolt-<name>: voltage in micro Volts. At runtime, the platform can pick a <name> and matching opp-microvolt-<name> property. HW: <name>: sun50iw-h6 speed0 speed1 speed2 Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> --- .../bindings/opp/sunxi-nvmem-cpufreq.txt | 168 ++++++++++++++++++ 1 file changed, 168 insertions(+) create mode 100644 Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt