diff mbox series

[1/5] mtd: rawnand: mtk: Correct low level time calculation of r/w cycle

Message ID 20190429063834.45967-2-xiaolei.li@mediatek.com (mailing list archive)
State New, archived
Headers show
Series MTK NAND driver improvements and fixes | expand

Commit Message

xiaolei li April 29, 2019, 6:38 a.m. UTC 
At present, the flow of calculating AC timing of read/write cycle in SDR
mode is that:
At first, calculate high hold time which is valid for both read and write
cycle using the max value between tREH_min and tWH_min.
Secondly, calculate WE# pulse width using tWP_min.
Thridly, calculate RE# pulse width using the bigger one between tREA_max
and tRP_min.

But NAND SPEC shows that Controller should also meet write/read cycle time.
That is write cycle time should be more than tWC_min and read cycle should
be more than tRC_min. Obviously, we do not achieve that now.

This patch corrects the low level time calculation to meet minimum
read/write cycle time required. After getting the high hold time, WE# low
level time will be promised to meet tWP_min and tWC_min requirement,
and RE# low level time will be promised to meet tREA_max, tRP_min and
tRC_min requirement.

Fixes: 93db446a424c ("mtd: nand: move raw NAND related code to the raw/ subdir")
Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
---
 drivers/mtd/nand/raw/mtk_nand.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

Comments

Miquel Raynal April 29, 2019, 9:03 a.m. UTC | #1 
Hi Xiaolei,

Xiaolei Li <xiaolei.li@mediatek.com> wrote on Mon, 29 Apr 2019 14:38:30
+0800:

> At present, the flow of calculating AC timing of read/write cycle in SDR
> mode is that:
> At first, calculate high hold time which is valid for both read and write
> cycle using the max value between tREH_min and tWH_min.
> Secondly, calculate WE# pulse width using tWP_min.
> Thridly, calculate RE# pulse width using the bigger one between tREA_max
> and tRP_min.
> 
> But NAND SPEC shows that Controller should also meet write/read cycle time.
> That is write cycle time should be more than tWC_min and read cycle should
> be more than tRC_min. Obviously, we do not achieve that now.
> 
> This patch corrects the low level time calculation to meet minimum
> read/write cycle time required. After getting the high hold time, WE# low
> level time will be promised to meet tWP_min and tWC_min requirement,
> and RE# low level time will be promised to meet tREA_max, tRP_min and
> tRC_min requirement.
> 
> Fixes: 93db446a424c ("mtd: nand: move raw NAND related code to the raw/ subdir")

This is definitely not the faulty patch. Please use --follow when
searching for the culprit, to avoid being blocked by the
renaming/moving work.

Also a Cc: stable might be worth.

> Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> ---
>  drivers/mtd/nand/raw/mtk_nand.c | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
> index b6b4602f5132..dd855f860a4b 100644
> --- a/drivers/mtd/nand/raw/mtk_nand.c
> +++ b/drivers/mtd/nand/raw/mtk_nand.c
> @@ -508,7 +508,7 @@ static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
>  {
>  	struct mtk_nfc *nfc = nand_get_controller_data(chip);
>  	const struct nand_sdr_timings *timings;
> -	u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt;
> +	u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst = 0, trlt = 0;
>  
>  	timings = nand_get_sdr_timings(conf);
>  	if (IS_ERR(timings))
> @@ -544,11 +544,19 @@ static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
>  	twh = DIV_ROUND_UP(twh * rate, 1000000) - 1;
>  	twh &= 0xf;
>  
> -	twst = timings->tWP_min / 1000;
> +	/* Calculate min low level timing for write cycle */
> +	if ((twh + 1) * 1000000 / rate < timings->tWC_min / 1000)
> +		twst = (timings->tWC_min / 1000 - (twh + 1) * 1000000 / rate)
> +			* 1000;
> +	twst = max(timings->tWP_min, twst) / 1000;
>  	twst = DIV_ROUND_UP(twst * rate, 1000000) - 1;
>  	twst &= 0xf;
>  
> -	trlt = max(timings->tREA_max, timings->tRP_min) / 1000;
> +	/* Calculate min low level timing for read cycle */
> +	if ((twh + 1) * 1000000 / rate < timings->tRC_min / 1000)
> +		trlt = (timings->tRC_min / 1000 - (twh + 1) * 1000000 / rate)
> +			* 1000;
> +	trlt = max3(trlt, timings->tREA_max, timings->tRP_min) / 1000;
>  	trlt = DIV_ROUND_UP(trlt * rate, 1000000) - 1;
>  	trlt &= 0xf;
>  


With this fixed,

Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>

Thanks,
Miquèl
xiaolei li April 29, 2019, 9:35 a.m. UTC | #2 
Hi Miquel,

Thanks for your review.


On Mon, 2019-04-29 at 11:03 +0200, Miquel Raynal wrote:
> Hi Xiaolei,
> 
> Xiaolei Li <xiaolei.li@mediatek.com> wrote on Mon, 29 Apr 2019 14:38:30
> +0800:
> 
> > At present, the flow of calculating AC timing of read/write cycle in SDR
> > mode is that:
> > At first, calculate high hold time which is valid for both read and write
> > cycle using the max value between tREH_min and tWH_min.
> > Secondly, calculate WE# pulse width using tWP_min.
> > Thridly, calculate RE# pulse width using the bigger one between tREA_max
> > and tRP_min.
> > 
> > But NAND SPEC shows that Controller should also meet write/read cycle time.
> > That is write cycle time should be more than tWC_min and read cycle should
> > be more than tRC_min. Obviously, we do not achieve that now.
> > 
> > This patch corrects the low level time calculation to meet minimum
> > read/write cycle time required. After getting the high hold time, WE# low
> > level time will be promised to meet tWP_min and tWC_min requirement,
> > and RE# low level time will be promised to meet tREA_max, tRP_min and
> > tRC_min requirement.
> > 
> > Fixes: 93db446a424c ("mtd: nand: move raw NAND related code to the raw/ subdir")
> 
> This is definitely not the faulty patch. Please use --follow when
> searching for the culprit, to avoid being blocked by the
> renaming/moving work.
Yes. This issue exists before raw/ sudir being created.

The faulty patch should be 'commit edfee3619c49 ("mtd: nand: mtk: add
->setup_data_interface() hook")' which cannot be found in git history
now.

Should I list it here?

> 
> Also a Cc: stable might be worth.
OK. Thanks.

> 
> > Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> > ---
> >  drivers/mtd/nand/raw/mtk_nand.c | 14 +++++++++++---
> >  1 file changed, 11 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
> > index b6b4602f5132..dd855f860a4b 100644
> > --- a/drivers/mtd/nand/raw/mtk_nand.c
> > +++ b/drivers/mtd/nand/raw/mtk_nand.c
> > @@ -508,7 +508,7 @@ static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
> >  {
> >  	struct mtk_nfc *nfc = nand_get_controller_data(chip);
> >  	const struct nand_sdr_timings *timings;
> > -	u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt;
> > +	u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst = 0, trlt = 0;
> >  
> >  	timings = nand_get_sdr_timings(conf);
> >  	if (IS_ERR(timings))
> > @@ -544,11 +544,19 @@ static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
> >  	twh = DIV_ROUND_UP(twh * rate, 1000000) - 1;
> >  	twh &= 0xf;
> >  
> > -	twst = timings->tWP_min / 1000;
> > +	/* Calculate min low level timing for write cycle */
> > +	if ((twh + 1) * 1000000 / rate < timings->tWC_min / 1000)
> > +		twst = (timings->tWC_min / 1000 - (twh + 1) * 1000000 / rate)
> > +			* 1000;
> > +	twst = max(timings->tWP_min, twst) / 1000;
> >  	twst = DIV_ROUND_UP(twst * rate, 1000000) - 1;
> >  	twst &= 0xf;
> >  
> > -	trlt = max(timings->tREA_max, timings->tRP_min) / 1000;
> > +	/* Calculate min low level timing for read cycle */
> > +	if ((twh + 1) * 1000000 / rate < timings->tRC_min / 1000)
> > +		trlt = (timings->tRC_min / 1000 - (twh + 1) * 1000000 / rate)
> > +			* 1000;
> > +	trlt = max3(trlt, timings->tREA_max, timings->tRP_min) / 1000;
> >  	trlt = DIV_ROUND_UP(trlt * rate, 1000000) - 1;
> >  	trlt &= 0xf;
> >  
> 
> 
> With this fixed,
> 
> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
> 
> Thanks,
> Miquèl

Thanks,
Xiaolei
Miquel Raynal April 29, 2019, 10:02 a.m. UTC | #3 
Hi xiaolei,

xiaolei li <xiaolei.li@mediatek.com> wrote on Mon, 29 Apr 2019 17:35:53
+0800:

> Hi Miquel,
> 
> Thanks for your review.
> 
> 
> On Mon, 2019-04-29 at 11:03 +0200, Miquel Raynal wrote:
> > Hi Xiaolei,
> > 
> > Xiaolei Li <xiaolei.li@mediatek.com> wrote on Mon, 29 Apr 2019 14:38:30
> > +0800:
> >   
> > > At present, the flow of calculating AC timing of read/write cycle in SDR
> > > mode is that:
> > > At first, calculate high hold time which is valid for both read and write
> > > cycle using the max value between tREH_min and tWH_min.
> > > Secondly, calculate WE# pulse width using tWP_min.
> > > Thridly, calculate RE# pulse width using the bigger one between tREA_max
> > > and tRP_min.
> > > 
> > > But NAND SPEC shows that Controller should also meet write/read cycle time.
> > > That is write cycle time should be more than tWC_min and read cycle should
> > > be more than tRC_min. Obviously, we do not achieve that now.
> > > 
> > > This patch corrects the low level time calculation to meet minimum
> > > read/write cycle time required. After getting the high hold time, WE# low
> > > level time will be promised to meet tWP_min and tWC_min requirement,
> > > and RE# low level time will be promised to meet tREA_max, tRP_min and
> > > tRC_min requirement.
> > > 
> > > Fixes: 93db446a424c ("mtd: nand: move raw NAND related code to the raw/ subdir")  
> > 
> > This is definitely not the faulty patch. Please use --follow when
> > searching for the culprit, to avoid being blocked by the
> > renaming/moving work.  
> Yes. This issue exists before raw/ sudir being created.
> 
> The faulty patch should be 'commit edfee3619c49 ("mtd: nand: mtk: add
> ->setup_data_interface() hook")' which cannot be found in git history  
> now.
> 
> Should I list it here?

What do you mean? This commit exists, I can actually "git show" it.


Thanks,
Miquèl
xiaolei li April 30, 2019, 12:59 a.m. UTC | #4 
On Mon, 2019-04-29 at 12:02 +0200, Miquel Raynal wrote:
> Hi xiaolei,
> 
> xiaolei li <xiaolei.li@mediatek.com> wrote on Mon, 29 Apr 2019 17:35:53
> +0800:
> 
> > Hi Miquel,
> > 
> > Thanks for your review.
> > 
> > 
> > On Mon, 2019-04-29 at 11:03 +0200, Miquel Raynal wrote:
> > > Hi Xiaolei,
> > > 
> > > Xiaolei Li <xiaolei.li@mediatek.com> wrote on Mon, 29 Apr 2019 14:38:30
> > > +0800:
> > >   
> > > > At present, the flow of calculating AC timing of read/write cycle in SDR
> > > > mode is that:
> > > > At first, calculate high hold time which is valid for both read and write
> > > > cycle using the max value between tREH_min and tWH_min.
> > > > Secondly, calculate WE# pulse width using tWP_min.
> > > > Thridly, calculate RE# pulse width using the bigger one between tREA_max
> > > > and tRP_min.
> > > > 
> > > > But NAND SPEC shows that Controller should also meet write/read cycle time.
> > > > That is write cycle time should be more than tWC_min and read cycle should
> > > > be more than tRC_min. Obviously, we do not achieve that now.
> > > > 
> > > > This patch corrects the low level time calculation to meet minimum
> > > > read/write cycle time required. After getting the high hold time, WE# low
> > > > level time will be promised to meet tWP_min and tWC_min requirement,
> > > > and RE# low level time will be promised to meet tREA_max, tRP_min and
> > > > tRC_min requirement.
> > > > 
> > > > Fixes: 93db446a424c ("mtd: nand: move raw NAND related code to the raw/ subdir")  
> > > 
> > > This is definitely not the faulty patch. Please use --follow when
> > > searching for the culprit, to avoid being blocked by the
> > > renaming/moving work.  
> > Yes. This issue exists before raw/ sudir being created.
> > 
> > The faulty patch should be 'commit edfee3619c49 ("mtd: nand: mtk: add
> > ->setup_data_interface() hook")' which cannot be found in git history  
> > now.
> > 
> > Should I list it here?
> 
> What do you mean? This commit exists, I can actually "git show" it.
> 
Sorry. I find it. Will fix it in next patch version.
Thanks.

> 
> Thanks,
> Miquèl
diff mbox series

Patch

diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
index b6b4602f5132..dd855f860a4b 100644
--- a/drivers/mtd/nand/raw/mtk_nand.c
+++ b/drivers/mtd/nand/raw/mtk_nand.c
@@ -508,7 +508,7 @@  static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
 {
 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
 	const struct nand_sdr_timings *timings;
-	u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt;
+	u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst = 0, trlt = 0;
 
 	timings = nand_get_sdr_timings(conf);
 	if (IS_ERR(timings))
@@ -544,11 +544,19 @@  static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline,
 	twh = DIV_ROUND_UP(twh * rate, 1000000) - 1;
 	twh &= 0xf;
 
-	twst = timings->tWP_min / 1000;
+	/* Calculate min low level timing for write cycle */
+	if ((twh + 1) * 1000000 / rate < timings->tWC_min / 1000)
+		twst = (timings->tWC_min / 1000 - (twh + 1) * 1000000 / rate)
+			* 1000;
+	twst = max(timings->tWP_min, twst) / 1000;
 	twst = DIV_ROUND_UP(twst * rate, 1000000) - 1;
 	twst &= 0xf;
 
-	trlt = max(timings->tREA_max, timings->tRP_min) / 1000;
+	/* Calculate min low level timing for read cycle */
+	if ((twh + 1) * 1000000 / rate < timings->tRC_min / 1000)
+		trlt = (timings->tRC_min / 1000 - (twh + 1) * 1000000 / rate)
+			* 1000;
+	trlt = max3(trlt, timings->tREA_max, timings->tRP_min) / 1000;
 	trlt = DIV_ROUND_UP(trlt * rate, 1000000) - 1;
 	trlt &= 0xf;