| Message ID | 1555426699-5340-2-git-send-email-fabien.dessenne@st.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | stm32 m4 remoteproc on STM32MP157c | expand |
On Tue, Apr 16, 2019 at 04:58:12PM +0200, Fabien Dessenne wrote: > Document the ML-AHB interconnect for stm32 SoCs. > > Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> > --- > .../devicetree/bindings/arm/stm32/mlahb.txt | 37 ++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/stm32/mlahb.txt > > diff --git a/Documentation/devicetree/bindings/arm/stm32/mlahb.txt b/Documentation/devicetree/bindings/arm/stm32/mlahb.txt > new file mode 100644 > index 0000000..a36458a > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/stm32/mlahb.txt > @@ -0,0 +1,37 @@ > +ML-AHB interconnect bindings > + > +These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects > +a Cortex-M subsystem with dedicated memories. > +The MCU SRAM and RETRAM memory parts can be accessed through different addresses > +(see "RAM aliases" in [1]) using different buses (see [2]) : balancing the > +Cortex-M firmware accesses among those ports allows to tune the system > +performance. > + > +[1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf > +[2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping > + > +Required properties: > +- compatible: should be "simple-bus" > +- dma-ranges: describes memory addresses translation between the local CPU and > + the remote Cortex-M processor. Each memory region, is declared with > + 3 parameters: > + - param 1: device base address (Cortex-M processor address) > + - param 2: physical base address (local CPU address) > + - param 3: size of the memory region. > + > +The Cortex-M remote processor accessed via the mlahb interconnect is described > +by a child node. > + > +Example: > +mlahb { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + dma-ranges = <0x00000000 0x38000000 0x10000>, > + <0x10000000 0x10000000 0x60000>, > + <0x30000000 0x30000000 0x60000>; > + > + m4_rproc: m4@0 { '0' is a cpu address given there's no 'ranges' now for translating cpu addresses. I think you want it to be 0x38000000 instead. > + ... > + }; > +}; > -- > 2.7.4 >
diff --git a/Documentation/devicetree/bindings/arm/stm32/mlahb.txt b/Documentation/devicetree/bindings/arm/stm32/mlahb.txt new file mode 100644 index 0000000..a36458a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/stm32/mlahb.txt @@ -0,0 +1,37 @@ +ML-AHB interconnect bindings + +These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects +a Cortex-M subsystem with dedicated memories. +The MCU SRAM and RETRAM memory parts can be accessed through different addresses +(see "RAM aliases" in [1]) using different buses (see [2]) : balancing the +Cortex-M firmware accesses among those ports allows to tune the system +performance. + +[1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf +[2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping + +Required properties: +- compatible: should be "simple-bus" +- dma-ranges: describes memory addresses translation between the local CPU and + the remote Cortex-M processor. Each memory region, is declared with + 3 parameters: + - param 1: device base address (Cortex-M processor address) + - param 2: physical base address (local CPU address) + - param 3: size of the memory region. + +The Cortex-M remote processor accessed via the mlahb interconnect is described +by a child node. + +Example: +mlahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x00000000 0x38000000 0x10000>, + <0x10000000 0x10000000 0x60000>, + <0x30000000 0x30000000 0x60000>; + + m4_rproc: m4@0 { + ... + }; +};
Document the ML-AHB interconnect for stm32 SoCs. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> --- .../devicetree/bindings/arm/stm32/mlahb.txt | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/stm32/mlahb.txt