Message ID | 20190502002138.10646-1-bjorn.andersson@linaro.org (mailing list archive) |
---|---|
State | Changes Requested, archived |
Headers | show |
Series | clk: gcc-qcs404: Add PCIe resets | expand |
On 02/05/2019 02:21, Bjorn Andersson wrote: > diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h > index 454b3f43f538..5959399fed2e 100644 > --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h > +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h > @@ -166,5 +166,12 @@ > #define GCC_PCIEPHY_0_PHY_BCR 12 > #define GCC_EMAC_BCR 13 > #define GCC_CDSP_RESTART 14 > +#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 14 Seems weird that there would be two names for the same entry at index 14?
On Thu, May 02, 2019 at 12:53:33PM +0200, Marc Gonzalez wrote: > On 02/05/2019 02:21, Bjorn Andersson wrote: > > > diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h > > index 454b3f43f538..5959399fed2e 100644 > > --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h > > +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h > > @@ -166,5 +166,12 @@ > > #define GCC_PCIEPHY_0_PHY_BCR 12 > > #define GCC_EMAC_BCR 13 > > #define GCC_CDSP_RESTART 14 > > +#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 14 > > Seems weird that there would be two names for the same entry at index 14? Changes since v2: - Rebased patch The proper tag in the subject should have been [PATCH v2]. This is most likely an issue caused by the rebase. Kind regards, Niklas
Quoting Niklas Cassel (2019-05-02 04:20:24) > On Thu, May 02, 2019 at 12:53:33PM +0200, Marc Gonzalez wrote: > > On 02/05/2019 02:21, Bjorn Andersson wrote: > > > > > diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h > > > index 454b3f43f538..5959399fed2e 100644 > > > --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h > > > +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h > > > @@ -166,5 +166,12 @@ > > > #define GCC_PCIEPHY_0_PHY_BCR 12 > > > #define GCC_EMAC_BCR 13 > > > #define GCC_CDSP_RESTART 14 > > > +#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 14 > > > > Seems weird that there would be two names for the same entry at index 14? > > Changes since v2: > - Rebased patch > > The proper tag in the subject should have been [PATCH v2]. > > This is most likely an issue caused by the rebase. > Please resend then.
On Thu 02 May 13:43 PDT 2019, Stephen Boyd wrote: > Quoting Niklas Cassel (2019-05-02 04:20:24) > > On Thu, May 02, 2019 at 12:53:33PM +0200, Marc Gonzalez wrote: > > > On 02/05/2019 02:21, Bjorn Andersson wrote: > > > > > > > diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h > > > > index 454b3f43f538..5959399fed2e 100644 > > > > --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h > > > > +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h > > > > @@ -166,5 +166,12 @@ > > > > #define GCC_PCIEPHY_0_PHY_BCR 12 > > > > #define GCC_EMAC_BCR 13 > > > > #define GCC_CDSP_RESTART 14 > > > > +#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 14 > > > > > > Seems weird that there would be two names for the same entry at index 14? > > > > Changes since v2: > > - Rebased patch > > > > The proper tag in the subject should have been [PATCH v2]. > > > > This is most likely an issue caused by the rebase. > > > > Please resend then. > Yeah, I screwed up the rebase. v4 is coming. Thanks Marc, Bjorn
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index a54807eb3b28..29cf464dd2c8 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -2766,6 +2766,13 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = { [GCC_PCIE_0_PHY_BCR] = { 0x3e004 }, [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 }, [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c }, + [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6}, + [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 }, + [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 }, + [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 }, + [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 }, + [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 }, + [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 }, [GCC_EMAC_BCR] = { 0x4e000 }, }; diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h index 454b3f43f538..5959399fed2e 100644 --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h @@ -166,5 +166,12 @@ #define GCC_PCIEPHY_0_PHY_BCR 12 #define GCC_EMAC_BCR 13 #define GCC_CDSP_RESTART 14 +#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 14 +#define GCC_PCIE_0_AHB_ARES 15 +#define GCC_PCIE_0_AXI_SLAVE_ARES 16 +#define GCC_PCIE_0_AXI_MASTER_ARES 17 +#define GCC_PCIE_0_CORE_STICKY_ARES 18 +#define GCC_PCIE_0_SLEEP_ARES 19 +#define GCC_PCIE_0_PIPE_ARES 20 #endif