| Message ID | 20190320094918.20234-9-rnayak@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | DVFS in the OPP core | expand |
On Wed, 20 Mar 2019 at 10:50, Rajendra Nayak <rnayak@codeaurora.org> wrote: > > Add the additional power domain and the OPP table for ufs on sdm845 > so the driver can set the appropriate performance state of the > power domain while setting the clock rate. > > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 20 +++++++++++++++++++- > 1 file changed, 19 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index 027ffe6e93e8..a3af4a1757b4 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -1140,6 +1140,21 @@ > }; > }; > > + ufs_opp_table: ufs-opp-table { > + compatible = "operating-points-v2"; > + > + opp-50000000 { > + opp-hz = /bits/ 64 <50000000>; > + required-opps = <&rpmhpd_opp_min_svs>; > + }; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_nom>; > + > + }; > + }; > + > ufs_mem_hc: ufshc@1d84000 { > compatible = "qcom,sdm845-ufshc", "qcom,ufshc", > "jedec,ufs-2.0"; > @@ -1148,7 +1163,7 @@ > phys = <&ufs_mem_phy_lanes>; > phy-names = "ufsphy"; > lanes-per-direction = <2>; > - power-domains = <&gcc UFS_PHY_GDSC>; > + power-domains = <&gcc UFS_PHY_GDSC>, <&rpmhpd SDM845_CX>; You probably want to use "power-domain-names" as well. [...] Kind regards Uffe
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 027ffe6e93e8..a3af4a1757b4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1140,6 +1140,21 @@ }; }; + ufs_opp_table: ufs-opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_nom>; + + }; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; @@ -1148,7 +1163,7 @@ phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; lanes-per-direction = <2>; - power-domains = <&gcc UFS_PHY_GDSC>; + power-domains = <&gcc UFS_PHY_GDSC>, <&rpmhpd SDM845_CX>; iommus = <&apps_smmu 0x100 0xf>; @@ -1170,6 +1185,9 @@ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + + operating-points-v2 = <&ufs_opp_table>; + freq-table-hz = <50000000 200000000>, <0 0>,
Add the additional power domain and the OPP table for ufs on sdm845 so the driver can set the appropriate performance state of the power domain while setting the clock rate. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-)