| Message ID | 20190522152016.10764-1-will.deacon@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: errata: Add workaround for Cortex-A76 erratum #1463225 | expand |
Hi,
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.1.4, v5.0.18, v4.19.45, v4.14.121, v4.9.178, v4.4.180, v3.18.140.
v5.1.4: Failed to apply! Possible dependencies:
3891ebccace18 ("arm64: Add sysfs vulnerability show for spectre-v1")
526e065dbca6d ("arm64: add sysfs vulnerability show for speculative store bypass")
52c6d145da15a ("arm64: debug: Remove unused return value from do_debug_exception()")
6989303a3b2d8 ("arm64: Apply ARM64_ERRATUM_1188873 to Neoverse-N1")
73f3816609594 ("arm64: Advertise mitigation of Spectre-v2, or lack thereof")
8c1e3d2bb44cb ("arm64: Always enable spectre-v2 vulnerability detection")
b9585f53bcf1a ("arm64: Advertise ARM64_HAS_DCPODP cpu feature")
d2532e27b5638 ("arm64: add sysfs vulnerability show for spectre-v2")
e5ce5e7267ddc ("arm64: Provide a command line to disable spectre_v2 mitigation")
v5.0.18: Failed to apply! Possible dependencies:
3891ebccace18 ("arm64: Add sysfs vulnerability show for spectre-v1")
526e065dbca6d ("arm64: add sysfs vulnerability show for speculative store bypass")
52c6d145da15a ("arm64: debug: Remove unused return value from do_debug_exception()")
6989303a3b2d8 ("arm64: Apply ARM64_ERRATUM_1188873 to Neoverse-N1")
73f3816609594 ("arm64: Advertise mitigation of Spectre-v2, or lack thereof")
8c1e3d2bb44cb ("arm64: Always enable spectre-v2 vulnerability detection")
b90d2b22afdc7 ("arm64: cpufeature: Add cpufeature for IRQ priority masking")
b9585f53bcf1a ("arm64: Advertise ARM64_HAS_DCPODP cpu feature")
d2532e27b5638 ("arm64: add sysfs vulnerability show for spectre-v2")
e5ce5e7267ddc ("arm64: Provide a command line to disable spectre_v2 mitigation")
v4.19.45: Failed to apply! Possible dependencies:
5ffdfaedfa0ab ("arm64: mm: Support Common Not Private translations")
6989303a3b2d8 ("arm64: Apply ARM64_ERRATUM_1188873 to Neoverse-N1")
86d0dd34eafff ("arm64: cpufeature: add feature for CRC32 instructions")
880f7cc47265e ("arm64: cpu_errata: Remove ARM64_MISMATCHED_CACHE_LINE_SIZE")
8f04e8e6e29c9 ("arm64: ssbd: Add support for PSTATE.SSBS rather than trapping to EL3")
95b861a4a6d94 ("arm64: arch_timer: Add workaround for ARM erratum 1188873")
ce8c80c536dac ("arm64: Add workaround for Cortex-A76 erratum 1286807")
d71be2b6c0e19 ("arm64: cpufeature: Detect SSBS and advertise to userspace")
e03a4e5bb7430 ("arm64: Add silicon-errata.txt entry for ARM erratum 1188873")
v4.14.121: Failed to apply! Possible dependencies:
0234bf885236a ("KVM: x86: introduce ISA specific SMM entry/exit callbacks")
14f0e5f8d97e6 ("ASoC: stm32: Add synchronization to SAI bindings")
282e45dc64d18 ("mtd: spi-nor: Add support for mr25h128")
3d345b5f7b2f6 ("ASoC: tfa9879: Add device tree bindings")
54839d012d5f9 ("dt-bindings: mmc: renesas_sdhi: add R-Car Gen[123] fallback compatibility strings")
5acc5c063196b ("KVM: Introduce KVM_MEMORY_ENCRYPT_OP ioctl")
5c2b4d5b78144 ("KVM: document KVM_CAP_S390_[BPB|PSW|GMAP|COW]")
631989303b06b ("Merge tag 'kvmarm-for-v4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD")
6989303a3b2d8 ("arm64: Apply ARM64_ERRATUM_1188873 to Neoverse-N1")
69eaedee411c1 ("KVM: Introduce KVM_MEMORY_ENCRYPT_{UN,}REG_REGION ioctl")
7bf14c28ee776 ("Merge branch 'x86/hyperv' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip")
86d0dd34eafff ("arm64: cpufeature: add feature for CRC32 instructions")
95b861a4a6d94 ("arm64: arch_timer: Add workaround for ARM erratum 1188873")
95e91ade69005 ("dt-bindings: mmc: renesas_sdhi: provide example in bindings documentation")
b07815d4eaf65 ("dt-bindings: mtd: add sst25wf040b and en25s64 to sip-nor list")
b0d40d2b22fe4 ("sched/isolation: Document isolcpus= boot parameter flags, mark it deprecated")
c1aea9196ef4f ("KVM: x86: hyperv: declare KVM_CAP_HYPERV_TLBFLUSH capability")
cc3d967f7e32c ("KVM: SVM: detect opening of SMI window using STGI intercept")
ce6a90027c10f ("platform/x86: Add driver to force WMI Thunderbolt controller power status")
ce8c80c536dac ("arm64: Add workaround for Cortex-A76 erratum 1286807")
d141babe42449 ("locking/lockdep: Add a boot parameter allowing unwind in cross-release and disable it by default")
d71be2b6c0e19 ("arm64: cpufeature: Detect SSBS and advertise to userspace")
d91ca84edeb04 ("mmc: dt-bindings: Add reg/source_cg/latch-ck for Mediatek MMC bindings")
da9a1446d248f ("KVM: s390: provide a capability for AIS state migration")
e03a4e5bb7430 ("arm64: Add silicon-errata.txt entry for ARM erratum 1188873")
faeb7833eee0d ("kvm: x86: hyperv: guest->host event signaling via eventfd")
v4.9.178: Failed to apply! Possible dependencies:
0c9d86833dfda ("KVM: s390: use defines for execution controls")
2583b848cad04 ("s390: report new vector facilities")
2ed4f9dd19c0f ("KVM: PPC: Book3S HV: Add capability to report possible virtual SMT modes")
3c313524605a6 ("KVM: PPC: Book3S HV: Allow userspace to set the desired SMT mode")
47a4693e1d3eb ("KVM: s390: introduce AIS capability")
4d5f2c04c8a46 ("KVM: s390: log runtime instrumentation enablement")
4e0b1ab72b8af ("KVM: s390: gs support for kvm guests")
57d7f939e7bdd ("s390: add no-execute support")
5c2b4d5b78144 ("KVM: document KVM_CAP_S390_[BPB|PSW|GMAP|COW]")
631989303b06b ("Merge tag 'kvmarm-for-v4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD")
6989303a3b2d8 ("arm64: Apply ARM64_ERRATUM_1188873 to Neoverse-N1")
6e01398fe4505 ("arm64: arch_timer: document Hisilicon erratum 161010101")
86d0dd34eafff ("arm64: cpufeature: add feature for CRC32 instructions")
916cda1aa1b41 ("s390: add a system call for guarded storage")
95b861a4a6d94 ("arm64: arch_timer: Add workaround for ARM erratum 1188873")
a679c547d19de ("KVM: s390: gaccess: add ESOP2 handling")
c1aea9196ef4f ("KVM: x86: hyperv: declare KVM_CAP_HYPERV_TLBFLUSH capability")
cd1836f583d78 ("KVM: s390: instruction-execution-protection support")
ce8c80c536dac ("arm64: Add workaround for Cortex-A76 erratum 1286807")
d1f7e8f85b512 ("s390: squash facilities_src.h into gen_facilities.c")
d3457c877b14a ("kvm: x86: hyperv: make VP_INDEX managed by userspace")
d71be2b6c0e19 ("arm64: cpufeature: Detect SSBS and advertise to userspace")
d9ff80f83ecbf ("arm64: Work around Falkor erratum 1009")
da9a1446d248f ("KVM: s390: provide a capability for AIS state migration")
e03a4e5bb7430 ("arm64: Add silicon-errata.txt entry for ARM erratum 1188873")
efc479e6900c2 ("kvm: x86: hyperv: add KVM_CAP_HYPERV_SYNIC2")
v4.4.180: Failed to apply! Possible dependencies:
06282fd2c2bf6 ("arm64: KVM: Implement vgic-v2 save/restore")
1431af367e52b ("arm64: KVM: Implement timer save/restore")
1bd37a6835bef ("iommu/arm-smmu: Workaround for ThunderX erratum #27704")
4e3e9b6997b24 ("iommu/arm-smmu: Add support for 16 bit VMID")
674e70127069f ("arm64: Document workaround for Cortex-A72 erratum #853709")
67b65a3fb8e65 ("iommu/arm-smmu: Differentiate specific implementations")
6989303a3b2d8 ("arm64: Apply ARM64_ERRATUM_1188873 to Neoverse-N1")
6d6ec20fcf283 ("arm64: KVM: Implement system register save/restore")
6e01398fe4505 ("arm64: arch_timer: document Hisilicon erratum 161010101")
75df1386557c2 ("iommu/arm-smmu: Invalidate TLBs properly")
8eb992674c9e6 ("arm64: KVM: Implement debug save/restore")
9cb9c9e5ba845 ("arm64: Documentation: add list of software workarounds for errata")
b97b66c14b96a ("arm64: KVM: Implement guest entry")
be901e9b15cd2 ("arm64: KVM: Implement the core world switch")
c76a0a6695c61 ("arm64: KVM: Add a HYP-specific header file")
ce8c80c536dac ("arm64: Add workaround for Cortex-A76 erratum 1286807")
e03a4e5bb7430 ("arm64: Add silicon-errata.txt entry for ARM erratum 1188873")
e086d912d4d78 ("iommu/arm-smmu: Convert ThunderX workaround to new method")
f0cfffc48cac5 ("iommu/arm-smmu: Work around MMU-500 prefetch errata")
f68d2b1b73cc3 ("arm64: KVM: Implement vgic-v3 save/restore")
v3.18.140: Failed to apply! Possible dependencies:
04597a65c5efc ("arm64: Track system support for mixed endian EL0")
104a0c02e8b19 ("arm64: Add workaround for Cavium erratum 27456")
1b907f46db074 ("arm64: kconfig: move emulation option under kernel features")
1bd37a6835bef ("iommu/arm-smmu: Workaround for ThunderX erratum #27704")
2d888f48e0561 ("arm64: Emulate SETEND for AArch32 tasks")
338d4f49d6f71 ("arm64: kernel: Add support for Privileged Access Never")
359b706473b47 ("arm64: Extract feature parsing code from cpu_errata.c")
518f7136244c1 ("iommu/arm-smmu: make use of generic LPAE allocator")
587064b610c70 ("arm64: Add framework for legacy instruction emulation")
674e70127069f ("arm64: Document workaround for Cortex-A72 erratum #853709")
67b65a3fb8e65 ("iommu/arm-smmu: Differentiate specific implementations")
6989303a3b2d8 ("arm64: Apply ARM64_ERRATUM_1188873 to Neoverse-N1")
6d4e11c5e2e8c ("irqchip/gicv3: Workaround for Cavium ThunderX erratum 23154")
6e01398fe4505 ("arm64: arch_timer: document Hisilicon erratum 161010101")
736d474f0fafd ("arm64: Consolidate hotplug notifier for instruction emulation")
859a732e4f713 ("iommu/arm-smmu: add support for iova_to_phys through ATS1PR")
870828e57b141 ("arm64: kernel: Move config_sctlr_el1")
94a9e04aa16ab ("arm64: alternative: Introduce feature for GICv3 CPU interface")
9b79f52d1a702 ("arm64: Add support for hooks to handle undefined instructions")
9cb9c9e5ba845 ("arm64: Documentation: add list of software workarounds for errata")
a720b41c41f5a ("iommu/arm-smmu: change IOMMU_EXEC to IOMMU_NOEXEC")
bd35a4adc4131 ("arm64: Port SWP/SWPB emulation support from arm")
c739dc83a0b6d ("arm64: lse: rename ARM64_CPU_FEAT_LSE_ATOMICS for consistency")
c752ce45b213d ("iommu/arm-smmu: add support for DOMAIN_ATTR_NESTING attribute")
c852f32058460 ("arm64: Emulate CP15 Barrier instructions")
c9453a3ab1a39 ("arm64: alternatives: fix pr_fmt string for consistency")
ce8c80c536dac ("arm64: Add workaround for Cortex-A76 erratum 1286807")
e03a4e5bb7430 ("arm64: Add silicon-errata.txt entry for ARM erratum 1188873")
ece1397cbc89c ("arm64: Add work around for Arm Cortex-A55 Erratum 1024718")
eeb1efbcb83c0 ("arm64: cpu_errata: Add capability to advertise Cortex-A73 erratum 858921")
f0cfffc48cac5 ("iommu/arm-smmu: Work around MMU-500 prefetch errata")
How should we proceed with this patch?
--
Thanks,
Sasha
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 68d9b74fd751..b29a32805ad0 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -62,6 +62,7 @@ stable kernels. | ARM | Cortex-A76 | #1165522 | ARM64_ERRATUM_1165522 | | ARM | Cortex-A76 | #1286807 | ARM64_ERRATUM_1286807 | | ARM | Neoverse-N1 | #1188873 | ARM64_ERRATUM_1188873 | +| ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 | | ARM | MMU-500 | #841119,#826419 | N/A | | | | | | | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 4780eb7af842..5d99f492869b 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -520,6 +520,24 @@ config ARM64_ERRATUM_1286807 If unsure, say Y. +config ARM64_ERRATUM_1463225 + bool "Cortex-A76: Software Step might prevent interrupt recognition" + default y + help + This option adds a workaround for Arm Cortex-A76 erratum 1463225. + + On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping + of a system call instruction (SVC) can prevent recognition of + subsequent interrupts when software stepping is disabled in the + exception handler of the system call and either kernel debugging + is enabled or VHE is in use. + + Work around the erratum by triggering a dummy step exception + when handling a system call from a task that is being stepped + in a VHE configuration of the kernel. + + If unsure, say Y. + config CAVIUM_ERRATUM_22375 bool "Cavium erratum 22375, 24313" default y diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index defdc67d9ab4..73faee64e498 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -62,7 +62,8 @@ #define ARM64_HAS_GENERIC_AUTH_IMP_DEF 41 #define ARM64_HAS_IRQ_PRIO_MASKING 42 #define ARM64_HAS_DCPODP 43 +#define ARM64_WORKAROUND_1463225 44 -#define ARM64_NCAPS 44 +#define ARM64_NCAPS 45 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index e88d4e7bdfc7..88ffefd83b7a 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -502,6 +502,24 @@ static const struct midr_range arm64_ssb_cpus[] = { {}, }; +#ifdef CONFIG_ARM64_ERRATUM_1463225 +DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa); + +static bool +has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry, + int scope) +{ + struct midr_range range; + u32 midr = read_cpuid_id(); + + /* Cortex-A76 r0p0 - r3p1 */ + range = MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1); + + WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); + return is_midr_in_range(midr, &range) && is_kernel_in_hyp_mode(); +} +#endif + static void __maybe_unused cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) { @@ -824,6 +842,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0), }, #endif +#ifdef CONFIG_ARM64_ERRATUM_1463225 + { + .desc = "ARM erratum 1463225", + .capability = ARM64_WORKAROUND_1463225, + .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, + .matches = has_cortex_a76_erratum_1463225, + }, +#endif { } }; diff --git a/arch/arm64/kernel/syscall.c b/arch/arm64/kernel/syscall.c index 5610ac01c1ec..871c739f060a 100644 --- a/arch/arm64/kernel/syscall.c +++ b/arch/arm64/kernel/syscall.c @@ -8,6 +8,7 @@ #include <linux/syscalls.h> #include <asm/daifflags.h> +#include <asm/debug-monitors.h> #include <asm/fpsimd.h> #include <asm/syscall.h> #include <asm/thread_info.h> @@ -60,6 +61,35 @@ static inline bool has_syscall_work(unsigned long flags) int syscall_trace_enter(struct pt_regs *regs); void syscall_trace_exit(struct pt_regs *regs); +#ifdef CONFIG_ARM64_ERRATUM_1463225 +DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa); + +static void cortex_a76_erratum_1463225_svc_handler(void) +{ + u32 reg, val; + + if (!unlikely(test_thread_flag(TIF_SINGLESTEP))) + return; + + if (!unlikely(this_cpu_has_cap(ARM64_WORKAROUND_1463225))) + return; + + __this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 1); + reg = read_sysreg(mdscr_el1); + val = reg | DBG_MDSCR_SS | DBG_MDSCR_KDE; + write_sysreg(val, mdscr_el1); + asm volatile("msr daifclr, #8"); + isb(); + + /* We will have taken a single-step exception by this point */ + + write_sysreg(reg, mdscr_el1); + __this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 0); +} +#else +static void cortex_a76_erratum_1463225_svc_handler(void) { } +#endif /* CONFIG_ARM64_ERRATUM_1463225 */ + static void el0_svc_common(struct pt_regs *regs, int scno, int sc_nr, const syscall_fn_t syscall_table[]) { @@ -68,6 +98,7 @@ static void el0_svc_common(struct pt_regs *regs, int scno, int sc_nr, regs->orig_x0 = regs->regs[0]; regs->syscallno = scno; + cortex_a76_erratum_1463225_svc_handler(); local_daif_restore(DAIF_PROCCTX); user_exit(); diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 0cb0e09995e1..a09f5bffb3c1 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -810,6 +810,36 @@ void __init hook_debug_fault_code(int nr, debug_fault_info[nr].name = name; } +#ifdef CONFIG_ARM64_ERRATUM_1463225 +DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa); + +static int __exception +cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs) +{ + if (user_mode(regs)) + return 0; + + if (!__this_cpu_read(__in_cortex_a76_erratum_1463225_wa)) + return 0; + + /* + * We've taken a dummy step exception from the kernel to ensure + * that interrupts are re-enabled on the syscall path. Return back + * to cortex_a76_erratum_1463225_svc_handler() with debug exceptions + * masked so that we can safely restore the mdscr and get on with + * handling the syscall. + */ + regs->pstate |= PSR_D_BIT; + return 1; +} +#else +static int __exception +cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs) +{ + return 0; +} +#endif /* CONFIG_ARM64_ERRATUM_1463225 */ + asmlinkage void __exception do_debug_exception(unsigned long addr_if_watchpoint, unsigned int esr, struct pt_regs *regs) @@ -817,6 +847,9 @@ asmlinkage void __exception do_debug_exception(unsigned long addr_if_watchpoint, const struct fault_info *inf = esr_to_debug_fault_info(esr); unsigned long pc = instruction_pointer(regs); + if (cortex_a76_erratum_1463225_debug_handler(regs)) + return 0; + /* * Tell lockdep we disabled irqs in entry.S. Do nothing if they were * already disabled to preserve the last enabled/disabled addresses.
Revisions of the Cortex-A76 CPU prior to r4p0 are affected by an erratum that can prevent interrupts from being taken when single-stepping. This patch implements a software workaround to prevent userspace from effectively being able to disable interrupts. Cc: <stable@vger.kernel.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> --- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 18 ++++++++++++++++++ arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/kernel/cpu_errata.c | 26 ++++++++++++++++++++++++++ arch/arm64/kernel/syscall.c | 31 +++++++++++++++++++++++++++++++ arch/arm64/mm/fault.c | 33 +++++++++++++++++++++++++++++++++ 6 files changed, 111 insertions(+), 1 deletion(-)