diff mbox series

drm/i915/perf: fix whitelist on Gen10+

Message ID 20190601225845.12600-1-lionel.g.landwerlin@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/perf: fix whitelist on Gen10+ | expand

Commit Message

Lionel Landwerlin June 1, 2019, 10:58 p.m. UTC
Gen10 added an additional NOA_WRITE register (high bits) and we forgot
to whitelist it for userspace.

Fixes: 95690a02fb5d96 ("drm/i915/perf: enable perf support on CNL")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 drivers/gpu/drm/i915/i915_perf.c | 1 +
 drivers/gpu/drm/i915/i915_reg.h  | 1 +
 2 files changed, 2 insertions(+)

Comments

Kenneth Graunke June 3, 2019, 7:03 p.m. UTC | #1
On Saturday, June 1, 2019 3:58:45 PM PDT Lionel Landwerlin wrote:
> Gen10 added an additional NOA_WRITE register (high bits) and we forgot
> to whitelist it for userspace.
> 
> Fixes: 95690a02fb5d96 ("drm/i915/perf: enable perf support on CNL")
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_perf.c | 1 +
>  drivers/gpu/drm/i915/i915_reg.h  | 1 +
>  2 files changed, 2 insertions(+)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index c4995d5a16d2..bebea5ba5c26 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3025,6 +3025,7 @@  static bool gen8_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
 static bool gen10_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
 {
 	return gen8_is_valid_mux_addr(dev_priv, addr) ||
+		addr == i915_mmio_reg_offset(GEN10_NOA_WRITE_HIGH) ||
 		(addr >= i915_mmio_reg_offset(OA_PERFCNT3_LO) &&
 		 addr <= i915_mmio_reg_offset(OA_PERFCNT4_HI));
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bba420aaa4ab..a631e747928d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1062,6 +1062,7 @@  static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 
 #define NOA_DATA	    _MMIO(0x986C)
 #define NOA_WRITE	    _MMIO(0x9888)
+#define GEN10_NOA_WRITE_HIGH _MMIO(0x9884)
 
 #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
 #define _GEN7_PIPEB_DE_LOAD_SL	0x71068