| Message ID | 86o92n82e1.fsf@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm: meson: global clean-up (use proper macros, update comments ...) | expand |
Julien Masson <jmasson@baylibre.com> writes: > This patch add new macro HHI_HDMI_PLL_CNTL_EN which is used to enable > HDMI PLL. > > Signed-off-by: Julien Masson <jmasson@baylibre.com> > --- > drivers/gpu/drm/meson/meson_vclk.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c > index e7c2b439d0f7..be6e152fc75a 100644 > --- a/drivers/gpu/drm/meson/meson_vclk.c > +++ b/drivers/gpu/drm/meson/meson_vclk.c > @@ -96,6 +96,7 @@ > #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ > > #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ > +#define HHI_HDMI_PLL_CNTL_EN BIT(30) > #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ > #define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ > #define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ > @@ -468,7 +469,7 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m, > > /* Enable and unreset */ > regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, > - 0x7 << 28, 0x4 << 28); > + 0x7 << 28, HHI_HDMI_PLL_CNTL_EN); still using a magic const for the mask. Can use GENMASK() for this? Kevin
On 25/06/2019 01:20, Kevin Hilman wrote: > Julien Masson <jmasson@baylibre.com> writes: > >> This patch add new macro HHI_HDMI_PLL_CNTL_EN which is used to enable >> HDMI PLL. >> >> Signed-off-by: Julien Masson <jmasson@baylibre.com> >> --- >> drivers/gpu/drm/meson/meson_vclk.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c >> index e7c2b439d0f7..be6e152fc75a 100644 >> --- a/drivers/gpu/drm/meson/meson_vclk.c >> +++ b/drivers/gpu/drm/meson/meson_vclk.c >> @@ -96,6 +96,7 @@ >> #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ >> >> #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ >> +#define HHI_HDMI_PLL_CNTL_EN BIT(30) >> #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ >> #define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ >> #define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ >> @@ -468,7 +469,7 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m, >> >> /* Enable and unreset */ >> regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, >> - 0x7 << 28, 0x4 << 28); >> + 0x7 << 28, HHI_HDMI_PLL_CNTL_EN); I'll do a pass on the PLL part since it needs much more work than a cleanup, it's ok for me. Neil > > still using a magic const for the mask. Can use GENMASK() for this? > > Kevin >
diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c index e7c2b439d0f7..be6e152fc75a 100644 --- a/drivers/gpu/drm/meson/meson_vclk.c +++ b/drivers/gpu/drm/meson/meson_vclk.c @@ -96,6 +96,7 @@ #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ +#define HHI_HDMI_PLL_CNTL_EN BIT(30) #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ #define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ #define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ @@ -468,7 +469,7 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m, /* Enable and unreset */ regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, - 0x7 << 28, 0x4 << 28); + 0x7 << 28, HHI_HDMI_PLL_CNTL_EN); /* Poll for lock bit */ regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
This patch add new macro HHI_HDMI_PLL_CNTL_EN which is used to enable HDMI PLL. Signed-off-by: Julien Masson <jmasson@baylibre.com> --- drivers/gpu/drm/meson/meson_vclk.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)