| Message ID | 20190613180931.65445-5-swboyd@chromium.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | tpm: Add driver for cr50 | expand |
On Thu, Jun 13, 2019 at 11:09:27AM -0700, Stephen Boyd wrote: > From: Andrey Pronin <apronin@chromium.org> > > Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50 > firmware. > > Signed-off-by: Andrey Pronin <apronin@chromium.org> > Cc: Rob Herring <robh+dt@kernel.org> > Signed-off-by: Stephen Boyd <swboyd@chromium.org> > --- > > This is a resend of https://lkml.kernel.org/r/1469757314-116169-2-git-send-email-apronin@chromium.org > with status removed. > > .../bindings/security/tpm/cr50_spi.txt | 19 +++++++++++++++++++ google,cr50.txt instead. With that, Reviewed-by: Rob Herring <robh@kernel.org> > 1 file changed, 19 insertions(+) > create mode 100644 Documentation/devicetree/bindings/security/tpm/cr50_spi.txt
diff --git a/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt new file mode 100644 index 000000000000..401f4ba281b7 --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt @@ -0,0 +1,19 @@ +* H1 Secure Microcontroller with Cr50 Firmware on SPI Bus. + +H1 Secure Microcontroller running Cr50 firmware provides several +functions, including TPM-like functionality. It communicates over +SPI using the FIFO protocol described in the PTP Spec, section 6. + +Required properties: +- compatible: Should be "google,cr50". +- spi-max-frequency: Maximum SPI frequency. + +Example: + +&spi0 { + cr50@0 { + compatible = "google,cr50"; + reg = <0>; + spi-max-frequency = <800000>; + }; +};