| Message ID | 20190716065551.27264-1-tao3.xu@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | KVM: x86: Enable user wait instructions | expand |
Ping for comments :) On 7/16/2019 2:55 PM, Tao Xu wrote: > UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions. > > UMONITOR arms address monitoring hardware using an address. A store > to an address within the specified address range triggers the > monitoring hardware to wake up the processor waiting in umwait. > > UMWAIT instructs the processor to enter an implementation-dependent > optimized state while monitoring a range of addresses. The optimized > state may be either a light-weight power/performance optimized state > (c0.1 state) or an improved power/performance optimized state > (c0.2 state). > > TPAUSE instructs the processor to enter an implementation-dependent > optimized state c0.1 or c0.2 state and wake up when time-stamp counter > reaches specified timeout. > > Availability of the user wait instructions is indicated by the presence > of the CPUID feature flag WAITPKG CPUID.0x07.0x0:ECX[5]. > > The patches enable the umonitor, umwait and tpause features in KVM. > Because umwait and tpause can put a (psysical) CPU into a power saving > state, by default we dont't expose it to kvm and enable it only when > guest CPUID has it. If the instruction causes a delay, the amount > of time delayed is called here the physical delay. The physical delay is > first computed by determining the virtual delay (the time to delay > relative to the VM’s timestamp counter). > > The release document ref below link: > Intel 64 and IA-32 Architectures Software Developer's Manual, > https://software.intel.com/sites/default/files/\ > managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf > > Changelog: > v8: > Add vmx_waitpkg_supported() helper (Sean) > Add an accessor to expose umwait_control_cached (Sean) > Set msr_ia32_umwait_control in vcpu_vmx u32 and raise #GP when > [63:32] is set when rdmsr. (Sean) > Introduce a common exit helper handle_unexpected_vmexit (Sean) > v7: > Add nested support for user wait instructions (Paolo) > Use the test on vmx->secondary_exec_control to replace > guest_cpuid_has (Paolo) > v6: > add check msr_info->host_initiated in get/set msr(Xiaoyao) > restore the atomic_switch_umwait_control_msr()(Xiaoyao) > > Tao Xu (3): > KVM: x86: Add support for user wait instructions > KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL > KVM: vmx: Introduce handle_unexpected_vmexit and handle WAITPKG vmexit > > arch/x86/include/asm/vmx.h | 1 + > arch/x86/include/uapi/asm/vmx.h | 6 ++- > arch/x86/kernel/cpu/umwait.c | 6 +++ > arch/x86/kvm/cpuid.c | 2 +- > arch/x86/kvm/vmx/capabilities.h | 6 +++ > arch/x86/kvm/vmx/nested.c | 5 ++ > arch/x86/kvm/vmx/vmx.c | 83 ++++++++++++++++++++++++++------- > arch/x86/kvm/vmx/vmx.h | 9 ++++ > arch/x86/kvm/x86.c | 1 + > 9 files changed, 101 insertions(+), 18 deletions(-) >
On 19/07/19 08:31, Tao Xu wrote: > Ping for comments :) Hi, I'll look at it for 5.4, right after the merge window. Paolo > On 7/16/2019 2:55 PM, Tao Xu wrote: >> UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions. >> >> UMONITOR arms address monitoring hardware using an address. A store >> to an address within the specified address range triggers the >> monitoring hardware to wake up the processor waiting in umwait. >> >> UMWAIT instructs the processor to enter an implementation-dependent >> optimized state while monitoring a range of addresses. The optimized >> state may be either a light-weight power/performance optimized state >> (c0.1 state) or an improved power/performance optimized state >> (c0.2 state). >> >> TPAUSE instructs the processor to enter an implementation-dependent >> optimized state c0.1 or c0.2 state and wake up when time-stamp counter >> reaches specified timeout. >> >> Availability of the user wait instructions is indicated by the presence >> of the CPUID feature flag WAITPKG CPUID.0x07.0x0:ECX[5]. >> >> The patches enable the umonitor, umwait and tpause features in KVM. >> Because umwait and tpause can put a (psysical) CPU into a power saving >> state, by default we dont't expose it to kvm and enable it only when >> guest CPUID has it. If the instruction causes a delay, the amount >> of time delayed is called here the physical delay. The physical delay is >> first computed by determining the virtual delay (the time to delay >> relative to the VM’s timestamp counter). >> >> The release document ref below link: >> Intel 64 and IA-32 Architectures Software Developer's Manual, >> https://software.intel.com/sites/default/files/\ >> managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf >> >> Changelog: >> v8: >> Add vmx_waitpkg_supported() helper (Sean) >> Add an accessor to expose umwait_control_cached (Sean) >> Set msr_ia32_umwait_control in vcpu_vmx u32 and raise #GP when >> [63:32] is set when rdmsr. (Sean) >> Introduce a common exit helper handle_unexpected_vmexit (Sean) >> v7: >> Add nested support for user wait instructions (Paolo) >> Use the test on vmx->secondary_exec_control to replace >> guest_cpuid_has (Paolo) >> v6: >> add check msr_info->host_initiated in get/set msr(Xiaoyao) >> restore the atomic_switch_umwait_control_msr()(Xiaoyao) >> >> Tao Xu (3): >> KVM: x86: Add support for user wait instructions >> KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL >> KVM: vmx: Introduce handle_unexpected_vmexit and handle WAITPKG vmexit >> >> arch/x86/include/asm/vmx.h | 1 + >> arch/x86/include/uapi/asm/vmx.h | 6 ++- >> arch/x86/kernel/cpu/umwait.c | 6 +++ >> arch/x86/kvm/cpuid.c | 2 +- >> arch/x86/kvm/vmx/capabilities.h | 6 +++ >> arch/x86/kvm/vmx/nested.c | 5 ++ >> arch/x86/kvm/vmx/vmx.c | 83 ++++++++++++++++++++++++++------- >> arch/x86/kvm/vmx/vmx.h | 9 ++++ >> arch/x86/kvm/x86.c | 1 + >> 9 files changed, 101 insertions(+), 18 deletions(-) >> >
On 7/20/2019 1:18 AM, Paolo Bonzini wrote: > On 19/07/19 08:31, Tao Xu wrote: >> Ping for comments :) > > Hi, I'll look at it for 5.4, right after the merge window. > > Paolo > Thank you Paolo! >> On 7/16/2019 2:55 PM, Tao Xu wrote: >>> UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions. >>> >>> UMONITOR arms address monitoring hardware using an address. A store >>> to an address within the specified address range triggers the >>> monitoring hardware to wake up the processor waiting in umwait. >>> >>> UMWAIT instructs the processor to enter an implementation-dependent >>> optimized state while monitoring a range of addresses. The optimized >>> state may be either a light-weight power/performance optimized state >>> (c0.1 state) or an improved power/performance optimized state >>> (c0.2 state). >>> >>> TPAUSE instructs the processor to enter an implementation-dependent >>> optimized state c0.1 or c0.2 state and wake up when time-stamp counter >>> reaches specified timeout. >>> >>> Availability of the user wait instructions is indicated by the presence >>> of the CPUID feature flag WAITPKG CPUID.0x07.0x0:ECX[5]. >>> >>> The patches enable the umonitor, umwait and tpause features in KVM. >>> Because umwait and tpause can put a (psysical) CPU into a power saving >>> state, by default we dont't expose it to kvm and enable it only when >>> guest CPUID has it. If the instruction causes a delay, the amount >>> of time delayed is called here the physical delay. The physical delay is >>> first computed by determining the virtual delay (the time to delay >>> relative to the VM’s timestamp counter). >>> >>> The release document ref below link: >>> Intel 64 and IA-32 Architectures Software Developer's Manual, >>> https://software.intel.com/sites/default/files/\ >>> managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf >>> >>> Changelog: >>> v8: >>> Add vmx_waitpkg_supported() helper (Sean) >>> Add an accessor to expose umwait_control_cached (Sean) >>> Set msr_ia32_umwait_control in vcpu_vmx u32 and raise #GP when >>> [63:32] is set when rdmsr. (Sean) >>> Introduce a common exit helper handle_unexpected_vmexit (Sean) >>> v7: >>> Add nested support for user wait instructions (Paolo) >>> Use the test on vmx->secondary_exec_control to replace >>> guest_cpuid_has (Paolo) >>> v6: >>> add check msr_info->host_initiated in get/set msr(Xiaoyao) >>> restore the atomic_switch_umwait_control_msr()(Xiaoyao) >>> >>> Tao Xu (3): >>> KVM: x86: Add support for user wait instructions >>> KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL >>> KVM: vmx: Introduce handle_unexpected_vmexit and handle WAITPKG vmexit >>> >>> arch/x86/include/asm/vmx.h | 1 + >>> arch/x86/include/uapi/asm/vmx.h | 6 ++- >>> arch/x86/kernel/cpu/umwait.c | 6 +++ >>> arch/x86/kvm/cpuid.c | 2 +- >>> arch/x86/kvm/vmx/capabilities.h | 6 +++ >>> arch/x86/kvm/vmx/nested.c | 5 ++ >>> arch/x86/kvm/vmx/vmx.c | 83 ++++++++++++++++++++++++++------- >>> arch/x86/kvm/vmx/vmx.h | 9 ++++ >>> arch/x86/kvm/x86.c | 1 + >>> 9 files changed, 101 insertions(+), 18 deletions(-) >>> >> >
On 7/20/2019 1:18 AM, Paolo Bonzini wrote: > On 19/07/19 08:31, Tao Xu wrote: >> Ping for comments :) > > Hi, I'll look at it for 5.4, right after the merge window. > > Paolo > Hi paolo, Linux 5.3 has released, could you review these patches. Thank you very much! Tao >> On 7/16/2019 2:55 PM, Tao Xu wrote: >>> UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions. >>> >>> UMONITOR arms address monitoring hardware using an address. A store >>> to an address within the specified address range triggers the >>> monitoring hardware to wake up the processor waiting in umwait. >>> >>> UMWAIT instructs the processor to enter an implementation-dependent >>> optimized state while monitoring a range of addresses. The optimized >>> state may be either a light-weight power/performance optimized state >>> (c0.1 state) or an improved power/performance optimized state >>> (c0.2 state). >>> >>> TPAUSE instructs the processor to enter an implementation-dependent >>> optimized state c0.1 or c0.2 state and wake up when time-stamp counter >>> reaches specified timeout. >>> >>> Availability of the user wait instructions is indicated by the presence >>> of the CPUID feature flag WAITPKG CPUID.0x07.0x0:ECX[5]. >>> >>> The patches enable the umonitor, umwait and tpause features in KVM. >>> Because umwait and tpause can put a (psysical) CPU into a power saving >>> state, by default we dont't expose it to kvm and enable it only when >>> guest CPUID has it. If the instruction causes a delay, the amount >>> of time delayed is called here the physical delay. The physical delay is >>> first computed by determining the virtual delay (the time to delay >>> relative to the VM’s timestamp counter). >>> >>> The release document ref below link: >>> Intel 64 and IA-32 Architectures Software Developer's Manual, >>> https://software.intel.com/sites/default/files/\ >>> managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf >>> >>> Changelog: >>> v8: >>> Add vmx_waitpkg_supported() helper (Sean) >>> Add an accessor to expose umwait_control_cached (Sean) >>> Set msr_ia32_umwait_control in vcpu_vmx u32 and raise #GP when >>> [63:32] is set when rdmsr. (Sean) >>> Introduce a common exit helper handle_unexpected_vmexit (Sean) >>> v7: >>> Add nested support for user wait instructions (Paolo) >>> Use the test on vmx->secondary_exec_control to replace >>> guest_cpuid_has (Paolo) >>> v6: >>> add check msr_info->host_initiated in get/set msr(Xiaoyao) >>> restore the atomic_switch_umwait_control_msr()(Xiaoyao) >>> >>> Tao Xu (3): >>> KVM: x86: Add support for user wait instructions >>> KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL >>> KVM: vmx: Introduce handle_unexpected_vmexit and handle WAITPKG vmexit >>> >>> arch/x86/include/asm/vmx.h | 1 + >>> arch/x86/include/uapi/asm/vmx.h | 6 ++- >>> arch/x86/kernel/cpu/umwait.c | 6 +++ >>> arch/x86/kvm/cpuid.c | 2 +- >>> arch/x86/kvm/vmx/capabilities.h | 6 +++ >>> arch/x86/kvm/vmx/nested.c | 5 ++ >>> arch/x86/kvm/vmx/vmx.c | 83 ++++++++++++++++++++++++++------- >>> arch/x86/kvm/vmx/vmx.h | 9 ++++ >>> arch/x86/kvm/x86.c | 1 + >>> 9 files changed, 101 insertions(+), 18 deletions(-) >>> >> >
On 16/09/19 03:28, Tao Xu wrote: > On 7/20/2019 1:18 AM, Paolo Bonzini wrote: >> On 19/07/19 08:31, Tao Xu wrote: >>> Ping for comments :) >> >> Hi, I'll look at it for 5.4, right after the merge window. >> >> Paolo >> > Hi paolo, > > Linux 5.3 has released, could you review these patches. Thank you very > much! > > Tao >>> On 7/16/2019 2:55 PM, Tao Xu wrote: >>>> UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions. >>>> >>>> UMONITOR arms address monitoring hardware using an address. A store >>>> to an address within the specified address range triggers the >>>> monitoring hardware to wake up the processor waiting in umwait. >>>> >>>> UMWAIT instructs the processor to enter an implementation-dependent >>>> optimized state while monitoring a range of addresses. The optimized >>>> state may be either a light-weight power/performance optimized state >>>> (c0.1 state) or an improved power/performance optimized state >>>> (c0.2 state). >>>> >>>> TPAUSE instructs the processor to enter an implementation-dependent >>>> optimized state c0.1 or c0.2 state and wake up when time-stamp counter >>>> reaches specified timeout. >>>> >>>> Availability of the user wait instructions is indicated by the presence >>>> of the CPUID feature flag WAITPKG CPUID.0x07.0x0:ECX[5]. >>>> >>>> The patches enable the umonitor, umwait and tpause features in KVM. >>>> Because umwait and tpause can put a (psysical) CPU into a power saving >>>> state, by default we dont't expose it to kvm and enable it only when >>>> guest CPUID has it. If the instruction causes a delay, the amount >>>> of time delayed is called here the physical delay. The physical >>>> delay is >>>> first computed by determining the virtual delay (the time to delay >>>> relative to the VM’s timestamp counter). >>>> >>>> The release document ref below link: >>>> Intel 64 and IA-32 Architectures Software Developer's Manual, >>>> https://software.intel.com/sites/default/files/\ >>>> managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf >>>> >>>> Changelog: >>>> v8: >>>> Add vmx_waitpkg_supported() helper (Sean) >>>> Add an accessor to expose umwait_control_cached (Sean) >>>> Set msr_ia32_umwait_control in vcpu_vmx u32 and raise #GP when >>>> [63:32] is set when rdmsr. (Sean) >>>> Introduce a common exit helper handle_unexpected_vmexit (Sean) >>>> v7: >>>> Add nested support for user wait instructions (Paolo) >>>> Use the test on vmx->secondary_exec_control to replace >>>> guest_cpuid_has (Paolo) >>>> v6: >>>> add check msr_info->host_initiated in get/set msr(Xiaoyao) >>>> restore the atomic_switch_umwait_control_msr()(Xiaoyao) >>>> >>>> Tao Xu (3): >>>> KVM: x86: Add support for user wait instructions >>>> KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL >>>> KVM: vmx: Introduce handle_unexpected_vmexit and handle WAITPKG >>>> vmexit >>>> >>>> arch/x86/include/asm/vmx.h | 1 + >>>> arch/x86/include/uapi/asm/vmx.h | 6 ++- >>>> arch/x86/kernel/cpu/umwait.c | 6 +++ >>>> arch/x86/kvm/cpuid.c | 2 +- >>>> arch/x86/kvm/vmx/capabilities.h | 6 +++ >>>> arch/x86/kvm/vmx/nested.c | 5 ++ >>>> arch/x86/kvm/vmx/vmx.c | 83 >>>> ++++++++++++++++++++++++++------- >>>> arch/x86/kvm/vmx/vmx.h | 9 ++++ >>>> arch/x86/kvm/x86.c | 1 + >>>> 9 files changed, 101 insertions(+), 18 deletions(-) >>>> >>> >> > Queued, thanks. Paolo