Message ID | 20190715214003.9714-5-paul@crapouillou.net (mailing list archive) |
---|---|
State | Mainlined |
Commit | 7176b6ac18469f63b3aa1f6e2997776ad81273b4 |
Headers | show |
Series | [1/5] MIPS: Disallow CPU_SUPPORTS_HUGEPAGES for XPA,EVA | expand |
Hello, Paul Cercueil wrote: > From: Daniel Silsby <dansilsby@gmail.com> > > During an update long ago to conform to 4-level page code, PMD_ORDER was > changed from 0 to 1, despite the fact that a PMD table is not used at > all in a 32-bit MIPS build. PMD_ORDER does not seem to be used in these > builds. Now, it matches PUD_ORDER, a nonsense #define to give a build > failure with informative error. > > The older commit that had redefined PMD_ORDER was > commit c6e8b587718c ("Update MIPS to use the 4-level pagetable code > thereby getting rid of the compacrapability headers.") > > Signed-off-by: Daniel Silsby <dansilsby@gmail.com> > Signed-off-by: Paul Cercueil <paul@crapouillou.net> Applied to mips-next. Thanks, Paul [ This message was auto-generated; if you believe anything is incorrect then please email paul.burton@mips.com to report it. ]
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h index b0a78c9b6434..e600570789f4 100644 --- a/arch/mips/include/asm/pgtable-32.h +++ b/arch/mips/include/asm/pgtable-32.h @@ -83,7 +83,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, #define PGD_ORDER (__PGD_ORDER >= 0 ? __PGD_ORDER : 0) #define PUD_ORDER aieeee_attempt_to_allocate_pud -#define PMD_ORDER 1 +#define PMD_ORDER aieeee_attempt_to_allocate_pmd #define PTE_ORDER 0 #define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2)