| Message ID | 20190730144020.3518-1-will@kernel.org (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 147b9635e6347104b91f48ca9dca61eb0fbf2a54 |
| Headers | show |
| Series | arm64: cpufeature: Fix feature comparison for CTR_EL0.{CWG, ERG} | expand |
On 07/30/2019 03:40 PM, Will Deacon wrote: > If CTR_EL0.{CWG,ERG} are 0b0000 then they must be interpreted to have > their architecturally maximum values, which defeats the use of > FTR_HIGHER_SAFE when sanitising CPU ID registers on heterogeneous > machines. > > Introduce FTR_HIGHER_OR_ZERO_SAFE so that these fields effectively > saturate at zero. > > Cc: Suzuki Poulose <suzuki.poulose@arm.com> > Fixes: 3c739b571084 ("arm64: Keep track of CPU feature registers") > Signed-off-by: Will Deacon <will@kernel.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
On Tue, Jul 30, 2019 at 03:40:20PM +0100, Will Deacon wrote: > If CTR_EL0.{CWG,ERG} are 0b0000 then they must be interpreted to have > their architecturally maximum values, which defeats the use of > FTR_HIGHER_SAFE when sanitising CPU ID registers on heterogeneous > machines. > > Introduce FTR_HIGHER_OR_ZERO_SAFE so that these fields effectively > saturate at zero. > > Cc: Suzuki Poulose <suzuki.poulose@arm.com> > Fixes: 3c739b571084 ("arm64: Keep track of CPU feature registers") > Signed-off-by: Will Deacon <will@kernel.org> > --- > arch/arm64/include/asm/cpufeature.h | 7 ++++--- > arch/arm64/kernel/cpufeature.c | 8 ++++++-- > 2 files changed, 10 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h > index 407e2bf23676..c96ffa4722d3 100644 > --- a/arch/arm64/include/asm/cpufeature.h > +++ b/arch/arm64/include/asm/cpufeature.h > @@ -35,9 +35,10 @@ > */ > > enum ftr_type { > - FTR_EXACT, /* Use a predefined safe value */ > - FTR_LOWER_SAFE, /* Smaller value is safe */ > - FTR_HIGHER_SAFE,/* Bigger value is safe */ > + FTR_EXACT, /* Use a predefined safe value */ > + FTR_LOWER_SAFE, /* Smaller value is safe */ > + FTR_HIGHER_SAFE, /* Bigger value is safe */ > + FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */ > }; Does this mean we've disproved the FUTEX_MAX_LOOPS conjecture? ;) FWIW: Acked-by: Mark Rutland <mark.rutland@arm.com> Mark. > > #define FTR_STRICT true /* SANITY check strict matching required */ > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index f29f36a65175..d19d14ba9ae4 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -225,8 +225,8 @@ static const struct arm64_ftr_bits ftr_ctr[] = { > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_CWG_SHIFT, 4, 0), > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_ERG_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), > /* > * Linux can handle differing I-cache policies. Userspace JITs will > @@ -468,6 +468,10 @@ static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, > case FTR_LOWER_SAFE: > ret = new < cur ? new : cur; > break; > + case FTR_HIGHER_OR_ZERO_SAFE: > + if (!cur || !new) > + break; > + /* Fallthrough */ > case FTR_HIGHER_SAFE: > ret = new > cur ? new : cur; > break; > -- > 2.11.0 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Tue, Jul 30, 2019 at 03:40:20PM +0100, Will Deacon wrote: > If CTR_EL0.{CWG,ERG} are 0b0000 then they must be interpreted to have > their architecturally maximum values, which defeats the use of > FTR_HIGHER_SAFE when sanitising CPU ID registers on heterogeneous > machines. > > Introduce FTR_HIGHER_OR_ZERO_SAFE so that these fields effectively > saturate at zero. > > Cc: Suzuki Poulose <suzuki.poulose@arm.com> > Fixes: 3c739b571084 ("arm64: Keep track of CPU feature registers") > Signed-off-by: Will Deacon <will@kernel.org> Queued for 5.3-rc3 (with a cc stable tag). Thanks.
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 407e2bf23676..c96ffa4722d3 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -35,9 +35,10 @@ */ enum ftr_type { - FTR_EXACT, /* Use a predefined safe value */ - FTR_LOWER_SAFE, /* Smaller value is safe */ - FTR_HIGHER_SAFE,/* Bigger value is safe */ + FTR_EXACT, /* Use a predefined safe value */ + FTR_LOWER_SAFE, /* Smaller value is safe */ + FTR_HIGHER_SAFE, /* Bigger value is safe */ + FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */ }; #define FTR_STRICT true /* SANITY check strict matching required */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index f29f36a65175..d19d14ba9ae4 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -225,8 +225,8 @@ static const struct arm64_ftr_bits ftr_ctr[] = { ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_CWG_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_ERG_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), /* * Linux can handle differing I-cache policies. Userspace JITs will @@ -468,6 +468,10 @@ static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, case FTR_LOWER_SAFE: ret = new < cur ? new : cur; break; + case FTR_HIGHER_OR_ZERO_SAFE: + if (!cur || !new) + break; + /* Fallthrough */ case FTR_HIGHER_SAFE: ret = new > cur ? new : cur; break;
If CTR_EL0.{CWG,ERG} are 0b0000 then they must be interpreted to have their architecturally maximum values, which defeats the use of FTR_HIGHER_SAFE when sanitising CPU ID registers on heterogeneous machines. Introduce FTR_HIGHER_OR_ZERO_SAFE so that these fields effectively saturate at zero. Cc: Suzuki Poulose <suzuki.poulose@arm.com> Fixes: 3c739b571084 ("arm64: Keep track of CPU feature registers") Signed-off-by: Will Deacon <will@kernel.org> --- arch/arm64/include/asm/cpufeature.h | 7 ++++--- arch/arm64/kernel/cpufeature.c | 8 ++++++-- 2 files changed, 10 insertions(+), 5 deletions(-)