diff mbox series

[v2,07/28] riscv: sifive_u: Set the minimum number of cpus to 2

Message ID 1565163924-18621-8-git-send-email-bmeng.cn@gmail.com (mailing list archive)
State New, archived
Headers show
Series riscv: sifive_u: Improve the emulation fidelity of sifive_u machine | expand

Commit Message

Bin Meng Aug. 7, 2019, 7:45 a.m. UTC
It is not useful if we only have one management CPU.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

Changes in v2:
- update the file header to indicate at least 2 harts are created

 hw/riscv/sifive_u.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Philippe Mathieu-Daudé Aug. 7, 2019, 9:46 a.m. UTC | #1
On 8/7/19 9:45 AM, Bin Meng wrote:
> It is not useful if we only have one management CPU.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> 
> ---
> 
> Changes in v2:
> - update the file header to indicate at least 2 harts are created
> 
>  hw/riscv/sifive_u.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 821f1d5..91f3c76 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -10,8 +10,8 @@
>   * 1) CLINT (Core Level Interruptor)
>   * 2) PLIC (Platform Level Interrupt Controller)
>   *
> - * This board currently generates devicetree dynamically that indicates at most
> - * five harts.
> + * This board currently generates devicetree dynamically that indicates at least
> + * two harts and up to five harts.
>   *
>   * This program is free software; you can redistribute it and/or modify it
>   * under the terms and conditions of the GNU General Public License,
> @@ -429,6 +429,8 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
>       * management CPU.
>       */
>      mc->max_cpus = 5;

I'm confuse this patch does not apply on top of v4.1.0-rc4.

Using #define makes these comments redundant, something like:

#define MANAGEMENT_CPU_COUNT 1
#define COMPUTE_CPU_COUNT 4

then you could use

  max_cpus = MANAGEMENT_CPU_COUNT + COMPUTE_CPU_COUNT

and

  min_cpus = MANAGEMENT_CPU_COUNT + 1.

> +    /* It is not useful if we only have one management CPU */
> +    mc->min_cpus = 2;
>  }
>  
>  DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
>
Bin Meng Aug. 7, 2019, 10:05 a.m. UTC | #2
On Wed, Aug 7, 2019 at 5:46 PM Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> On 8/7/19 9:45 AM, Bin Meng wrote:
> > It is not useful if we only have one management CPU.
> >
> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> >
> > ---
> >
> > Changes in v2:
> > - update the file header to indicate at least 2 harts are created
> >
> >  hw/riscv/sifive_u.c | 6 ++++--
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> > index 821f1d5..91f3c76 100644
> > --- a/hw/riscv/sifive_u.c
> > +++ b/hw/riscv/sifive_u.c
> > @@ -10,8 +10,8 @@
> >   * 1) CLINT (Core Level Interruptor)
> >   * 2) PLIC (Platform Level Interrupt Controller)
> >   *
> > - * This board currently generates devicetree dynamically that indicates at most
> > - * five harts.
> > + * This board currently generates devicetree dynamically that indicates at least
> > + * two harts and up to five harts.
> >   *
> >   * This program is free software; you can redistribute it and/or modify it
> >   * under the terms and conditions of the GNU General Public License,
> > @@ -429,6 +429,8 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
> >       * management CPU.
> >       */
> >      mc->max_cpus = 5;
>
> I'm confuse this patch does not apply on top of v4.1.0-rc4.
>

I suspect you need apply the whole series, not this single one due to
patch dependencies in this series?

> Using #define makes these comments redundant, something like:
>
> #define MANAGEMENT_CPU_COUNT 1
> #define COMPUTE_CPU_COUNT 4
>
> then you could use
>
>   max_cpus = MANAGEMENT_CPU_COUNT + COMPUTE_CPU_COUNT
>
> and
>
>   min_cpus = MANAGEMENT_CPU_COUNT + 1.
>

Good idea! I will change that in the next version. Thanks!

Regards,
Bin
diff mbox series

Patch

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 821f1d5..91f3c76 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -10,8 +10,8 @@ 
  * 1) CLINT (Core Level Interruptor)
  * 2) PLIC (Platform Level Interrupt Controller)
  *
- * This board currently generates devicetree dynamically that indicates at most
- * five harts.
+ * This board currently generates devicetree dynamically that indicates at least
+ * two harts and up to five harts.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -429,6 +429,8 @@  static void riscv_sifive_u_machine_init(MachineClass *mc)
      * management CPU.
      */
     mc->max_cpus = 5;
+    /* It is not useful if we only have one management CPU */
+    mc->min_cpus = 2;
 }
 
 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)