| Message ID | 20190808160005.10325-8-hch@lst.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/8] dma-mapping: provide a better default ->get_required_mask | expand |
Helger, or other parisc folks: can you take a look at this patch in particular and the series in general? Thanks!
On Thu, 2019-08-08 at 19:00 +0300, Christoph Hellwig wrote: > parisc is the only architecture that sets ARCH_NO_COHERENT_DMA_MMAP > when an MMU is enabled. AFAIK this is because parisc CPUs use VIVT > caches, We're actually VIPT but the same principle applies. > which means exporting normally cachable memory to userspace is > relatively dangrous due to cache aliasing. > > But normally cachable memory is only allocated by dma_alloc_coherent > on parisc when using the sba_iommu or ccio_iommu drivers, so just > remove the .mmap implementation for them so that we don't have to set > ARCH_NO_COHERENT_DMA_MMAP, which I plan to get rid of. So I don't think this is quite right. We have three architectural variants essentially (hidden behind about 12 cpu types): 1. pa70xx: These can't turn off page caching, so they were the non coherent problem case 2. pa71xx: These can manufacture coherent memory simply by turning off the cache on a per page basis 3. pa8xxx: these have a full cache flush coherence mechanism. (I might have this slightly wrong: I vaguely remember the pa71xxlc variants have some weird cache quirks for DMA as well) So I think pa70xx we can't mmap. pa71xx we can provided we mark the page as uncached ... which should already have happened in the allocate and pa8xxx which can always mmap dma memory without any special tricks. James
On Thu, Aug 15, 2019 at 10:25:52AM +0100, James Bottomley wrote: > > which means exporting normally cachable memory to userspace is > > relatively dangrous due to cache aliasing. > > > > But normally cachable memory is only allocated by dma_alloc_coherent > > on parisc when using the sba_iommu or ccio_iommu drivers, so just > > remove the .mmap implementation for them so that we don't have to set > > ARCH_NO_COHERENT_DMA_MMAP, which I plan to get rid of. > > So I don't think this is quite right. We have three architectural > variants essentially (hidden behind about 12 cpu types): > > 1. pa70xx: These can't turn off page caching, so they were the non > coherent problem case > 2. pa71xx: These can manufacture coherent memory simply by turning off > the cache on a per page basis > 3. pa8xxx: these have a full cache flush coherence mechanism. > > (I might have this slightly wrong: I vaguely remember the pa71xxlc > variants have some weird cache quirks for DMA as well) > > So I think pa70xx we can't mmap. pa71xx we can provided we mark the > page as uncached ... which should already have happened in the allocate > and pa8xxx which can always mmap dma memory without any special tricks. Except for the different naming scheme vs the code this matches my assumptions. In the code we have three cases (and a fourth EISA case mention in comments, but not actually implemented as far as I can tell): arch/parisc/kernel/pci-dma.c says in the top of file comments: ** AFAIK, all PA7100LC and PA7300LC platforms can use this code. and the handles two different case. for cpu_type == pcxl or pcxl2 it maps the memory as uncached for dma_alloc_coherent, and for all other cpu types it fails the coherent allocations. In addition to that there are the ccio and sba iommu drivers, of which according to your above comment one is always present for pa8xxx. Which brings us back to this patch, which ensures that no cacheable memory is exported to userspace by removing ->mmap from ccio and sba. It then enabled dma_mmap_coherent for the pcxl or pcxl2 case that allocates uncached memory, which dma_mmap_coherent does not work because dma_alloc_coherent already failed for the !pcxl && !pcxl2 and thus there is no memory to mmap. So if the description is too confusing please suggest a better one, I'm a little lost between all these code names and product names (arch/parisc/include/asm/dma-mapping.h uses yet another set).
Does my explanation from Thursday make sense or is it completely off? Does the patch description need some update to be less confusing to those used to different terminology? On Thu, Aug 15, 2019 at 12:50:02PM +0200, Christoph Hellwig wrote: > Except for the different naming scheme vs the code this matches my > assumptions. > > In the code we have three cases (and a fourth EISA case mention in > comments, but not actually implemented as far as I can tell): > > arch/parisc/kernel/pci-dma.c says in the top of file comments: > > ** AFAIK, all PA7100LC and PA7300LC platforms can use this code. > > and the handles two different case. for cpu_type == pcxl or pcxl2 > it maps the memory as uncached for dma_alloc_coherent, and for all > other cpu types it fails the coherent allocations. > > In addition to that there are the ccio and sba iommu drivers, of which > according to your above comment one is always present for pa8xxx. > > Which brings us back to this patch, which ensures that no cacheable > memory is exported to userspace by removing ->mmap from ccio and sba. > It then enabled dma_mmap_coherent for the pcxl or pcxl2 case that > allocates uncached memory, which dma_mmap_coherent does not work > because dma_alloc_coherent already failed for the !pcxl && !pcxl2 > and thus there is no memory to mmap. > > So if the description is too confusing please suggest a better > one, I'm a little lost between all these code names and product > names (arch/parisc/include/asm/dma-mapping.h uses yet another set). ---end quoted text---
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig index 6d732e451071..e9dd88b7f81e 100644 --- a/arch/parisc/Kconfig +++ b/arch/parisc/Kconfig @@ -52,7 +52,6 @@ config PARISC select GENERIC_SCHED_CLOCK select HAVE_UNSTABLE_SCHED_CLOCK if SMP select GENERIC_CLOCKEVENTS - select ARCH_NO_COHERENT_DMA_MMAP select CPU_NO_EFFICIENT_FFS select NEED_DMA_MAP_STATE select NEED_SG_DMA_LENGTH diff --git a/drivers/parisc/ccio-dma.c b/drivers/parisc/ccio-dma.c index 1d7125d29bee..ad290f79983b 100644 --- a/drivers/parisc/ccio-dma.c +++ b/drivers/parisc/ccio-dma.c @@ -1024,7 +1024,6 @@ static const struct dma_map_ops ccio_ops = { .unmap_page = ccio_unmap_page, .map_sg = ccio_map_sg, .unmap_sg = ccio_unmap_sg, - .mmap = dma_common_mmap, .get_sgtable = dma_common_get_sgtable, }; diff --git a/drivers/parisc/sba_iommu.c b/drivers/parisc/sba_iommu.c index fa4df65b7e28..ed50502cc65a 100644 --- a/drivers/parisc/sba_iommu.c +++ b/drivers/parisc/sba_iommu.c @@ -1084,7 +1084,6 @@ static const struct dma_map_ops sba_ops = { .unmap_page = sba_unmap_page, .map_sg = sba_map_sg, .unmap_sg = sba_unmap_sg, - .mmap = dma_common_mmap, .get_sgtable = dma_common_get_sgtable, };
parisc is the only architecture that sets ARCH_NO_COHERENT_DMA_MMAP when an MMU is enabled. AFAIK this is because parisc CPUs use VIVT caches, which means exporting normally cachable memory to userspace is relatively dangrous due to cache aliasing. But normally cachable memory is only allocated by dma_alloc_coherent on parisc when using the sba_iommu or ccio_iommu drivers, so just remove the .mmap implementation for them so that we don't have to set ARCH_NO_COHERENT_DMA_MMAP, which I plan to get rid of. Signed-off-by: Christoph Hellwig <hch@lst.de> --- arch/parisc/Kconfig | 1 - drivers/parisc/ccio-dma.c | 1 - drivers/parisc/sba_iommu.c | 1 - 3 files changed, 3 deletions(-)