| Message ID | 20190820032311.6506-6-samuel@sholland.org (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Allwinner sunxi message box support | expand |
Hi, On Mon, Aug 19, 2019 at 10:23:06PM -0500, Samuel Holland wrote: > The A80 SoC contains a message box that can be used to send messages and > interrupts back and forth between the ARM application CPUs and the ARISC > coprocessor. Add a device tree node for it. > > Signed-off-by: Samuel Holland <samuel@sholland.org> I think you mentionned that crust has been tested only on the A64 and the H3/H5, did you test the mailbox on those other SoCs as well? Thanks! Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
Hi, On 8/20/19 3:15 AM, Maxime Ripard wrote: > On Mon, Aug 19, 2019 at 10:23:06PM -0500, Samuel Holland wrote: >> The A80 SoC contains a message box that can be used to send messages and >> interrupts back and forth between the ARM application CPUs and the ARISC >> coprocessor. Add a device tree node for it. >> >> Signed-off-by: Samuel Holland <samuel@sholland.org> > > I think you mentionned that crust has been tested only on the A64 and > the H3/H5, did you test the mailbox on those other SoCs as well? No, I only have A64/H3/H5, and recently H6, hardware to test. I've looked through the manuals to verify that the registers are all the same, but I haven't run the driver on earlier SoCs. On 32-bit SoCs, where there's no other user of SRAM A2, it should be easy to get the toy firmware running. All you should need to do is: 1) Update the MMIO base/clock addresses in drivers/msgbox/sunxi-msgbox.c 2) Update the load address in platform/sun50i/include/platform/memory.h 3) Load the firmware to SRAM A2 (can be done from a U-Boot shell) 4) Initialize the reset vector (algorithm is in tools/test.c:109) 5) Deassert AR100 reset (again, these last two steps can be done from U-Boot) Thanks, Samuel
Hi, On Tue, Aug 20, 2019 at 08:17:49AM -0500, Samuel Holland wrote: > On 8/20/19 3:15 AM, Maxime Ripard wrote: > > On Mon, Aug 19, 2019 at 10:23:06PM -0500, Samuel Holland wrote: > >> The A80 SoC contains a message box that can be used to send messages and > >> interrupts back and forth between the ARM application CPUs and the ARISC > >> coprocessor. Add a device tree node for it. > >> > >> Signed-off-by: Samuel Holland <samuel@sholland.org> > > > > I think you mentionned that crust has been tested only on the A64 and > > the H3/H5, did you test the mailbox on those other SoCs as well? > > No, I only have A64/H3/H5, and recently H6, hardware to test. I've looked > through the manuals to verify that the registers are all the same, but I haven't > run the driver on earlier SoCs. I'd rather not merge them until they've been properly tested. We've had some surprises with the documentation in the past :/ Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index c34d505c7efe..844a265dbd0e 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -318,6 +318,16 @@ }; }; + msgbox: mailbox@803000 { + compatible = "allwinner,sun9i-a80-msgbox", + "allwinner,sun6i-a31-msgbox"; + reg = <0x00803000 0x1000>; + clocks = <&ccu CLK_BUS_MSGBOX>; + resets = <&ccu RST_BUS_MSGBOX>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + }; + gmac: ethernet@830000 { compatible = "allwinner,sun7i-a20-gmac"; reg = <0x00830000 0x1054>;
The A80 SoC contains a message box that can be used to send messages and interrupts back and forth between the ARM application CPUs and the ARISC coprocessor. Add a device tree node for it. Signed-off-by: Samuel Holland <samuel@sholland.org> --- arch/arm/boot/dts/sun9i-a80.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)