Message ID | 20190829161635.25067-1-jbrunet@baylibre.com (mailing list archive) |
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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id q13sm3915424wmq.30.2019.08.29.09.16.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2019 09:16:39 -0700 (PDT) From: Jerome Brunet <jbrunet@baylibre.com> To: Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <marc.zyngier@arm.com>, Kevin Hilman <khilman@baylibre.com> Subject: [PATCH 0/2] irqchip/meson-gpio: add sm1 support Date: Thu, 29 Aug 2019 18:16:33 +0200 Message-Id: <20190829161635.25067-1-jbrunet@baylibre.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-Patchwork-Bot: notify X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190829_091641_386954_D4F4EDEF X-CRM114-Status: UNSURE ( 7.60 ) X-CRM114-Notice: Please train this message. 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Series |
irqchip/meson-gpio: add sm1 support
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On 29/08/2019 17:16, Jerome Brunet wrote: > This patchset adds support for the new sm1 SoC family in the Amlogic gpio > interrupt controller. > > Jerome Brunet (2): > dt-bindings: interrupt-controller: new binding for the meson sm1 SoCs > irqchip/meson-gpio: Add support for meson sm1 SoCs > > .../amlogic,meson-gpio-intc.txt | 1 + > drivers/irqchip/irq-meson-gpio.c | 52 ++++++++++++++----- > 2 files changed, 39 insertions(+), 14 deletions(-) > Applied to irqchip-next. M.