diff mbox series

ARM: ARM_ERRATA_775420: Spelling s/date/data/

Message ID 20190828133151.20585-1-geert+renesas@glider.be (mailing list archive)
State Mainlined
Commit cb73737ea1d27181f5c4bfb1288e97f3e8a4abc7
Headers show
Series ARM: ARM_ERRATA_775420: Spelling s/date/data/ | expand

Commit Message

Geert Uytterhoeven Aug. 28, 2019, 1:31 p.m. UTC
Caching dates is never a good idea ;-)

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Simon Horman Aug. 31, 2019, 7:29 a.m. UTC | #1
On Wed, Aug 28, 2019 at 03:31:51PM +0200, Geert Uytterhoeven wrote:
> Caching dates is never a good idea ;-)
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

> ---
>  arch/arm/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index dcf46f0e45c24a5f..eb18279a63027c08 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1040,7 +1040,7 @@ config ARM_ERRATA_775420
>         depends on CPU_V7
>         help
>  	 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
> -	 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
> +	 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
>  	 operation aborts with MMU exception, it might cause the processor
>  	 to deadlock. This workaround puts DSB before executing ISB if
>  	 an abort may occur on cache maintenance.
> -- 
> 2.17.1
>
diff mbox series

Patch

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dcf46f0e45c24a5f..eb18279a63027c08 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1040,7 +1040,7 @@  config ARM_ERRATA_775420
        depends on CPU_V7
        help
 	 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
-	 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
+	 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
 	 operation aborts with MMU exception, it might cause the processor
 	 to deadlock. This workaround puts DSB before executing ISB if
 	 an abort may occur on cache maintenance.