| Message ID | 20190910190513.21160-1-palmer@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 | expand |
On Wed, 11 Sep 2019 at 09:24, Palmer Dabbelt <palmer@sifive.com> wrote: > > The following changes since commit 89ea03a7dc83ca36b670ba7f787802791fcb04b1: > > Merge remote-tracking branch 'remotes/huth-gitlab/tags/m68k-pull-2019-09-07' into staging (2019-09-09 09:48:34 +0100) > > are available in the Git repository at: > > git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.2-sf1 > > for you to fetch changes up to 1b2d0961bfaaa2db3a237f53273527b6c5e3498a: > > target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point (2019-09-10 06:08:42 -0700) > > ---------------------------------------------------------------- > RISC-V Patches for the 4.2 Soft Freeze, Part 1 > > This contains quite a few patches that I'd like to target for 4.2. > They're mostly emulation fixes for the sifive_u board, which now much > more closely matches the hardware and can therefor run the same fireware > as what gets loaded onto the board. Additional user-visible > improvements include: > > * support for loading initrd files from the command line into Linux, via > /chosen/linux,initrd-{start,end} device tree nodes. > * The conversion of LOG_TRACE to trace events. > * The addition of clock DT nodes for our uart and ethernet. > > This also includes some preliminary work for the H extension patches, > but does not include the H extension patches as I haven't had time to > review them yet. > > This passes my OE boot test on 32-bit and 64-bit virt machines, as well > as a 64-bit upstream Linux boot on the sifive_u machine. > Hi; this fails 'make check' on all platforms: MALLOC_PERTURB_=${MALLOC_PERTURB_:-$(( ${RANDOM:-0} % 255 + 1))} QTEST_QEMU_BINARY=riscv32-softmmu/qemu-system-riscv32 QTEST_QEMU_IMG=qemu-img t ests/qom-test -m=quick -k --tap < /dev/null | ./scripts/tap-driver.pl --test-name="qom-test" PASS 1 qom-test /riscv32/qom/spike PASS 2 qom-test /riscv32/qom/virt PASS 3 qom-test /riscv32/qom/none PASS 4 qom-test /riscv32/qom/spike_v1.10 qemu-system-riscv32: Invalid SMP CPUs 1. The min CPUs supported by machine 'sifive_u' is 2 socket_accept failed: Resource temporarily unavailable ** ERROR:/home/petmay01/linaro/qemu-for-merges/tests/libqtest.c:266:qtest_init_without_qmp_handshake: assertion failed: (s->fd >= 0 && s->qmp_fd >= 0) /home/petmay01/linaro/qemu-for-merges/tests/libqtest.c:135: kill_qemu() tried to terminate QEMU process but encountered exit status 1 ERROR - Bail out! ERROR:/home/petmay01/linaro/qemu-for-merges/tests/libqtest.c:266:qtest_init_without_qmp_handshake: assertion failed: (s->fd >= 0 && s->qmp_fd >= 0) Aborted (core dumped) /home/petmay01/linaro/qemu-for-merges/tests/Makefile.include:900: recipe for target 'check-qtest-riscv32' failed thanks -- PMM
On Fri, 13 Sep 2019 02:17:32 PDT (-0700), Peter Maydell wrote: > On Wed, 11 Sep 2019 at 09:24, Palmer Dabbelt <palmer@sifive.com> wrote: >> >> The following changes since commit 89ea03a7dc83ca36b670ba7f787802791fcb04b1: >> >> Merge remote-tracking branch 'remotes/huth-gitlab/tags/m68k-pull-2019-09-07' into staging (2019-09-09 09:48:34 +0100) >> >> are available in the Git repository at: >> >> git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.2-sf1 >> >> for you to fetch changes up to 1b2d0961bfaaa2db3a237f53273527b6c5e3498a: >> >> target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point (2019-09-10 06:08:42 -0700) >> >> ---------------------------------------------------------------- >> RISC-V Patches for the 4.2 Soft Freeze, Part 1 >> >> This contains quite a few patches that I'd like to target for 4.2. >> They're mostly emulation fixes for the sifive_u board, which now much >> more closely matches the hardware and can therefor run the same fireware >> as what gets loaded onto the board. Additional user-visible >> improvements include: >> >> * support for loading initrd files from the command line into Linux, via >> /chosen/linux,initrd-{start,end} device tree nodes. >> * The conversion of LOG_TRACE to trace events. >> * The addition of clock DT nodes for our uart and ethernet. >> >> This also includes some preliminary work for the H extension patches, >> but does not include the H extension patches as I haven't had time to >> review them yet. >> >> This passes my OE boot test on 32-bit and 64-bit virt machines, as well >> as a 64-bit upstream Linux boot on the sifive_u machine. >> > > Hi; this fails 'make check' on all platforms: > > MALLOC_PERTURB_=${MALLOC_PERTURB_:-$(( ${RANDOM:-0} % 255 + 1))} > QTEST_QEMU_BINARY=riscv32-softmmu/qemu-system-riscv32 > QTEST_QEMU_IMG=qemu-img t > ests/qom-test -m=quick -k --tap < /dev/null | ./scripts/tap-driver.pl > --test-name="qom-test" > PASS 1 qom-test /riscv32/qom/spike > PASS 2 qom-test /riscv32/qom/virt > PASS 3 qom-test /riscv32/qom/none > PASS 4 qom-test /riscv32/qom/spike_v1.10 > qemu-system-riscv32: Invalid SMP CPUs 1. The min CPUs supported by > machine 'sifive_u' is 2 > socket_accept failed: Resource temporarily unavailable > ** > ERROR:/home/petmay01/linaro/qemu-for-merges/tests/libqtest.c:266:qtest_init_without_qmp_handshake: > assertion failed: (s->fd >= 0 && s->qmp_fd >= 0) > /home/petmay01/linaro/qemu-for-merges/tests/libqtest.c:135: > kill_qemu() tried to terminate QEMU process but encountered exit > status 1 > ERROR - Bail out! > ERROR:/home/petmay01/linaro/qemu-for-merges/tests/libqtest.c:266:qtest_init_without_qmp_handshake: > assertion failed: (s->fd >= 0 && s->qmp_fd >= 0) > Aborted (core dumped) > /home/petmay01/linaro/qemu-for-merges/tests/Makefile.include:900: > recipe for target 'check-qtest-riscv32' failed Sorry about that, I ran the tests on the wrong branch. I'll submit another PR with the issue fixed.
The following changes since commit 89ea03a7dc83ca36b670ba7f787802791fcb04b1: Merge remote-tracking branch 'remotes/huth-gitlab/tags/m68k-pull-2019-09-07' into staging (2019-09-09 09:48:34 +0100) are available in the Git repository at: git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.2-sf1 for you to fetch changes up to 1b2d0961bfaaa2db3a237f53273527b6c5e3498a: target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point (2019-09-10 06:08:42 -0700) ---------------------------------------------------------------- RISC-V Patches for the 4.2 Soft Freeze, Part 1 This contains quite a few patches that I'd like to target for 4.2. They're mostly emulation fixes for the sifive_u board, which now much more closely matches the hardware and can therefor run the same fireware as what gets loaded onto the board. Additional user-visible improvements include: * support for loading initrd files from the command line into Linux, via /chosen/linux,initrd-{start,end} device tree nodes. * The conversion of LOG_TRACE to trace events. * The addition of clock DT nodes for our uart and ethernet. This also includes some preliminary work for the H extension patches, but does not include the H extension patches as I haven't had time to review them yet. This passes my OE boot test on 32-bit and 64-bit virt machines, as well as a 64-bit upstream Linux boot on the sifive_u machine. ---------------------------------------------------------------- Alistair Francis (5): riscv: plic: Remove unused interrupt functions target/riscv: Create function to test if FP is enabled target/riscv: Update the Hypervisor CSRs to v0.4 target/riscv: Fix mstatus dirty mask target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point Atish Patra (1): target/riscv: Use both register name and ABI name Bin Meng (36): riscv: rv32: Root page table address can be larger than 32-bit riscv: Add a helper routine for finding firmware riscv: Resolve full path of the given bios image riscv: hmp: Add a command to show virtual memory mappings riscv: sifive_test: Add reset functionality riscv: hw: Remove duplicated "hw/hw.h" inclusion riscv: hw: Remove superfluous "linux, phandle" property riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell riscv: hw: Remove not needed PLIC properties in device tree riscv: hw: Change create_fdt() to return void riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead riscv: hw: Remove the unnecessary include of target/riscv/cpu.h riscv: roms: Remove executable attribute of opensbi images riscv: sifive_u: Remove the unnecessary include of prci header riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming riscv: sifive_e: prci: Update the PRCI register block size riscv: sifive_e: Drop sifive_mmio_emulate() riscv: Add a sifive_cpu.h to include both E and U cpu type defines riscv: hart: Extract hart realize to a separate routine riscv: hart: Add a "hartid-base" property to RISC-V hart array riscv: sifive_u: Set the minimum number of cpus to 2 riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC riscv: sifive_u: Update PLIC hart topology configuration string riscv: sifive: Implement PRCI model for FU540 riscv: sifive_u: Generate hfclk and rtcclk nodes riscv: sifive_u: Add PRCI block to the SoC riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes riscv: sifive_u: Update UART base addresses and IRQs riscv: sifive_u: Change UART node name in device tree riscv: roms: Update default bios for sifive_u machine riscv: sifive: Implement a model for SiFive FU540 OTP riscv: sifive_u: Instantiate OTP memory with a serial number riscv: sifive_u: Fix broken GEM support riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet riscv: sifive_u: Update model and compatible strings in device tree Guenter Roeck (3): riscv: sifive_u: Add support for loading initrd riscv: sivive_u: Add dummy serial clock and aliases entry for uart riscv: sifive_u: Fix clock-names property for ethernet node Philippe Mathieu-Daudé (2): target/riscv/pmp: Restrict priviledged PMP to system-mode emulation target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events hmp-commands-info.hx | 2 +- hw/riscv/Kconfig | 2 + hw/riscv/Makefile.objs | 4 +- hw/riscv/boot.c | 26 ++- hw/riscv/riscv_hart.c | 34 ++-- hw/riscv/sifive_e.c | 27 ++- hw/riscv/sifive_e_prci.c | 124 +++++++++++++ hw/riscv/sifive_plic.c | 12 -- hw/riscv/sifive_prci.c | 125 ------------- hw/riscv/sifive_test.c | 11 +- hw/riscv/sifive_u.c | 252 +++++++++++++++++++-------- hw/riscv/sifive_u_otp.c | 191 ++++++++++++++++++++ hw/riscv/sifive_u_prci.c | 169 ++++++++++++++++++ hw/riscv/sifive_uart.c | 10 +- hw/riscv/spike.c | 1 - hw/riscv/virt.c | 40 ++--- include/hw/riscv/boot.h | 1 + include/hw/riscv/riscv_hart.h | 1 + include/hw/riscv/sifive_cpu.h | 31 ++++ include/hw/riscv/sifive_e.h | 7 +- include/hw/riscv/sifive_e_prci.h | 71 ++++++++ include/hw/riscv/sifive_plic.h | 3 - include/hw/riscv/sifive_prci.h | 71 -------- include/hw/riscv/sifive_test.h | 3 +- include/hw/riscv/sifive_u.h | 31 ++-- include/hw/riscv/sifive_u_otp.h | 80 +++++++++ include/hw/riscv/sifive_u_prci.h | 91 ++++++++++ pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 40968 -> 45064 bytes pc-bios/opensbi-riscv64-virt-fw_jump.bin | Bin roms/Makefile | 4 +- target/riscv/Makefile.objs | 7 +- target/riscv/cpu.c | 19 +- target/riscv/cpu.h | 6 +- target/riscv/cpu_bits.h | 35 ++-- target/riscv/cpu_helper.c | 20 ++- target/riscv/csr.c | 22 +-- target/riscv/monitor.c | 229 ++++++++++++++++++++++++ target/riscv/pmp.c | 35 ++-- target/riscv/trace-events | 6 + 40 files changed, 1361 insertions(+), 442 deletions(-) create mode 100644 hw/riscv/sifive_e_prci.c delete mode 100644 hw/riscv/sifive_prci.c create mode 100644 hw/riscv/sifive_u_otp.c create mode 100644 hw/riscv/sifive_u_prci.c create mode 100644 include/hw/riscv/sifive_cpu.h create mode 100644 include/hw/riscv/sifive_e_prci.h delete mode 100644 include/hw/riscv/sifive_prci.h create mode 100644 include/hw/riscv/sifive_u_otp.h create mode 100644 include/hw/riscv/sifive_u_prci.h mode change 100755 => 100644 pc-bios/opensbi-riscv32-virt-fw_jump.bin mode change 100755 => 100644 pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin mode change 100755 => 100644 pc-bios/opensbi-riscv64-virt-fw_jump.bin create mode 100644 target/riscv/monitor.c