| Message ID | 20190913115312.12943-3-andrew.murray@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | coresight: etm4x: save/restore ETMv4 context across CPU low power states | expand |
On Fri, 13 Sep 2019 12:53:11 +0100, Andrew Murray wrote: > Some coresight components, because of choices made during hardware > integration, require their state to be saved and restored across CPU low > power states. > > The software has no reliable method of detecting when save/restore is > required thus let's add a binding to inform the kernel. > > Signed-off-by: Andrew Murray <andrew.murray@arm.com> > Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > --- > Documentation/devicetree/bindings/arm/coresight.txt | 9 +++++++++ > 1 file changed, 9 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index fcc3bacfd8bc..d02c42d21f2f 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -87,6 +87,15 @@ its hardware characteristcs. * port or ports: see "Graph bindings for Coresight" below. +* Optional properties for all components: + + * arm,coresight-loses-context-with-cpu : boolean. Indicates that the + hardware will lose register context on CPU power down (e.g. CPUIdle). + An example of where this may be needed are systems which contain a + coresight component and CPU in the same power domain. When the CPU + powers down the coresight component also powers down and loses its + context. This property is currently only used for the ETM 4.x driver. + * Optional properties for ETM/PTMs: * arm,cp14: must be present if the system accesses ETM/PTM management