| Message ID | 20190909231445.23815-1-radhakrishna.sripada@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] drm/i915/tgl: Implement Wa_1409142259 | expand |
On 9/9/19 4:14 PM, Radhakrishna Sripada wrote: > Disable CPS aware color pipe by setting chicken bit. > > BSpec: 52890 > HSDES: 1409142259 > > v2: Move WA to ctx WA's(Daniele) > > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Stuart Summers <stuart.summers@intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Daniele > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > drivers/gpu/drm/i915/i915_reg.h | 1 + > 2 files changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 243d3f77be13..95ef2f1dfdbb 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -567,6 +567,9 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, > static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, > struct i915_wa_list *wal) > { > + /* Wa_1409142259 */ > + WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, > + GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); > } > > static void > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 006cffd56be2..53e07882efb7 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7668,6 +7668,7 @@ enum { > > #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) > #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11) > + #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9) > > #define HIZ_CHICKEN _MMIO(0x7018) > # define CHV_HZ_8X8_MODE_IN_1X (1 << 15) >
Hi Daniele, Thanks for the review. Can you help me merge this pathc? Thanks, Radhakrishna(RK) Sripada > -----Original Message----- > From: Ceraolo Spurio, Daniele > Sent: Wednesday, September 11, 2019 11:12 AM > To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; intel- > gfx@lists.freedesktop.org > Cc: Summers, Stuart <stuart.summers@intel.com>; Roper, Matthew D > <matthew.d.roper@intel.com> > Subject: Re: [PATCH v2] drm/i915/tgl: Implement Wa_1409142259 > > > > On 9/9/19 4:14 PM, Radhakrishna Sripada wrote: > > Disable CPS aware color pipe by setting chicken bit. > > > > BSpec: 52890 > > HSDES: 1409142259 > > > > v2: Move WA to ctx WA's(Daniele) > > > > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > > Cc: Stuart Summers <stuart.summers@intel.com> > > Cc: Matt Roper <matthew.d.roper@intel.com> > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > > Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > > Daniele > > > --- > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > 2 files changed, 4 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > index 243d3f77be13..95ef2f1dfdbb 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > @@ -567,6 +567,9 @@ static void icl_ctx_workarounds_init(struct > intel_engine_cs *engine, > > static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, > > struct i915_wa_list *wal) > > { > > + /* Wa_1409142259 */ > > + WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, > > + GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); > > } > > > > static void > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h index 006cffd56be2..53e07882efb7 > > 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -7668,6 +7668,7 @@ enum { > > > > #define GEN11_COMMON_SLICE_CHICKEN3 > _MMIO(0x7304) > > #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11) > > + #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9) > > > > #define HIZ_CHICKEN > _MMIO(0x7018) > > # define CHV_HZ_8X8_MODE_IN_1X (1 << > 15) > >
On Wed, Sep 18, 2019 at 04:05:06PM -0700, Sripada, Radhakrishna wrote: > Hi Daniele, > > Thanks for the review. Can you help me merge this pathc? > > Thanks, > Radhakrishna(RK) Sripada Applied to dinq. Thanks for the patch and review. Matt > > > -----Original Message----- > > From: Ceraolo Spurio, Daniele > > Sent: Wednesday, September 11, 2019 11:12 AM > > To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; intel- > > gfx@lists.freedesktop.org > > Cc: Summers, Stuart <stuart.summers@intel.com>; Roper, Matthew D > > <matthew.d.roper@intel.com> > > Subject: Re: [PATCH v2] drm/i915/tgl: Implement Wa_1409142259 > > > > > > > > On 9/9/19 4:14 PM, Radhakrishna Sripada wrote: > > > Disable CPS aware color pipe by setting chicken bit. > > > > > > BSpec: 52890 > > > HSDES: 1409142259 > > > > > > v2: Move WA to ctx WA's(Daniele) > > > > > > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > > > Cc: Stuart Summers <stuart.summers@intel.com> > > > Cc: Matt Roper <matthew.d.roper@intel.com> > > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > > > > Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > > > > Daniele > > > > > --- > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > > 2 files changed, 4 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > index 243d3f77be13..95ef2f1dfdbb 100644 > > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > @@ -567,6 +567,9 @@ static void icl_ctx_workarounds_init(struct > > intel_engine_cs *engine, > > > static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, > > > struct i915_wa_list *wal) > > > { > > > + /* Wa_1409142259 */ > > > + WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, > > > + GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); > > > } > > > > > > static void > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > > b/drivers/gpu/drm/i915/i915_reg.h index 006cffd56be2..53e07882efb7 > > > 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -7668,6 +7668,7 @@ enum { > > > > > > #define GEN11_COMMON_SLICE_CHICKEN3 > > _MMIO(0x7304) > > > #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11) > > > + #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9) > > > > > > #define HIZ_CHICKEN > > _MMIO(0x7018) > > > # define CHV_HZ_8X8_MODE_IN_1X (1 << > > 15) > > >
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 243d3f77be13..95ef2f1dfdbb 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -567,6 +567,9 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) { + /* Wa_1409142259 */ + WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, + GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); } static void diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 006cffd56be2..53e07882efb7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7668,6 +7668,7 @@ enum { #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11) + #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9) #define HIZ_CHICKEN _MMIO(0x7018) # define CHV_HZ_8X8_MODE_IN_1X (1 << 15)
Disable CPS aware color pipe by setting chicken bit. BSpec: 52890 HSDES: 1409142259 v2: Move WA to ctx WA's(Daniele) Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Stuart Summers <stuart.summers@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 4 insertions(+)