| Message ID | 1568869559-28611-2-git-send-email-Anson.Huang@nxp.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | a6a40d5688f2264afd40574ee1c92e5f824b34ba |
| Headers | show |
| Series | [1/3] arm64: dts: imx8mq: Use correct clock for usdhc's ipg clk | expand |
Hi Anson, I have a question, that is not directly related to this patch. I see that for the usdhc1 and usdhc3 nodes, there is an 'assigned-clock' and 'assigned-clock-rates' property but not for usdhc2. The same applies to the mx8mq and mx8mn dtsi file. Is there any reason for this? If not can you fix it? Thanks, Frieder On 19.09.19 07:05, Anson Huang wrote: > On i.MX8MM, usdhc's ipg clock is from IMX8MM_CLK_IPG_ROOT, > assign it explicitly instead of using IMX8MM_CLK_DUMMY. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index 7c4dcce..8aafad2 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -694,7 +694,7 @@ > compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; > reg = <0x30b40000 0x10000>; > interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&clk IMX8MM_CLK_DUMMY>, > + clocks = <&clk IMX8MM_CLK_IPG_ROOT>, > <&clk IMX8MM_CLK_NAND_USDHC_BUS>, > <&clk IMX8MM_CLK_USDHC1_ROOT>; > clock-names = "ipg", "ahb", "per"; > @@ -710,7 +710,7 @@ > compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; > reg = <0x30b50000 0x10000>; > interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&clk IMX8MM_CLK_DUMMY>, > + clocks = <&clk IMX8MM_CLK_IPG_ROOT>, > <&clk IMX8MM_CLK_NAND_USDHC_BUS>, > <&clk IMX8MM_CLK_USDHC2_ROOT>; > clock-names = "ipg", "ahb", "per"; > @@ -724,7 +724,7 @@ > compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; > reg = <0x30b60000 0x10000>; > interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&clk IMX8MM_CLK_DUMMY>, > + clocks = <&clk IMX8MM_CLK_IPG_ROOT>, > <&clk IMX8MM_CLK_NAND_USDHC_BUS>, > <&clk IMX8MM_CLK_USDHC3_ROOT>; > clock-names = "ipg", "ahb", "per"; >
Hi, Schrempf > Hi Anson, > > I have a question, that is not directly related to this patch. > I see that for the usdhc1 and usdhc3 nodes, there is an 'assigned-clock' > and 'assigned-clock-rates' property but not for usdhc2. The same applies to > the mx8mq and mx8mn dtsi file. > > Is there any reason for this? If not can you fix it? This patch series is NOT related to 'assigned-clock' or 'assigned-clock-rates' property, it is just for correcting clock source according to reference manual, the 'ipg' clock is from system's IPG_ROOT clock according to reference manual CCM chapter, using DUMMY clock is NOT a good option, the 'ipg' clock is supposed to be the clock for accessing register, and it should NOT be DUMMY if we know what exactly the clock source is used. Thanks, Anson
Hi Anson, On 19.09.19 11:31, Anson Huang wrote: > Hi, Schrempf > >> Hi Anson, >> >> I have a question, that is not directly related to this patch. >> I see that for the usdhc1 and usdhc3 nodes, there is an 'assigned-clock' >> and 'assigned-clock-rates' property but not for usdhc2. The same applies to >> the mx8mq and mx8mn dtsi file. >> >> Is there any reason for this? If not can you fix it? > > This patch series is NOT related to 'assigned-clock' or 'assigned-clock-rates' > property, That's exactly what I'm saying. To not cause more confusion, I have sent a message in a new thread: http://lists.infradead.org/pipermail/linux-arm-kernel/2019-September/681426.html > it is just for correcting clock source according to reference manual, > the 'ipg' clock is from system's IPG_ROOT clock according to reference manual CCM > chapter, using DUMMY clock is NOT a good option, the 'ipg' clock is supposed > to be the clock for accessing register, and it should NOT be DUMMY if we know > what exactly the clock source is used. That's probably right and I didn't mean to question the patch at all. Thanks, Frieder
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 7c4dcce..8aafad2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -694,7 +694,7 @@ compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b40000 0x10000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_DUMMY>, + clocks = <&clk IMX8MM_CLK_IPG_ROOT>, <&clk IMX8MM_CLK_NAND_USDHC_BUS>, <&clk IMX8MM_CLK_USDHC1_ROOT>; clock-names = "ipg", "ahb", "per"; @@ -710,7 +710,7 @@ compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b50000 0x10000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_DUMMY>, + clocks = <&clk IMX8MM_CLK_IPG_ROOT>, <&clk IMX8MM_CLK_NAND_USDHC_BUS>, <&clk IMX8MM_CLK_USDHC2_ROOT>; clock-names = "ipg", "ahb", "per"; @@ -724,7 +724,7 @@ compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b60000 0x10000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_DUMMY>, + clocks = <&clk IMX8MM_CLK_IPG_ROOT>, <&clk IMX8MM_CLK_NAND_USDHC_BUS>, <&clk IMX8MM_CLK_USDHC3_ROOT>; clock-names = "ipg", "ahb", "per";
On i.MX8MM, usdhc's ipg clock is from IMX8MM_CLK_IPG_ROOT, assign it explicitly instead of using IMX8MM_CLK_DUMMY. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)