| Message ID | 20190926145621.9090-6-anshuman.gupta@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | DC3CO Support for TGL | expand |
On Thu, Sep 26, 2019 at 08:26:19PM +0530, Anshuman Gupta wrote: > Disallow DC3CO state before PSR2 exit. > Store dc3co_exitline from crtc state to psr dev_priv > structure to use it easily whenever it requires. > > v1: Moved calling of tgl_enable_psr2_transcoder_exitline() to > intel_psr_enable(). [Imre] > v2: Moved tgl_psr2_deep_sleep_enable/disable function to > the patches where they are getting used and used dc3co_exitline > check instead of TGL check. [Imre] > > Cc: Jani Nikula <jani.nikula@intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Cc: Animesh Manna <animesh.manna@intel.com> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Please merge this patch to the next one. > --- > drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++++++ > drivers/gpu/drm/i915/i915_drv.h | 1 + > 2 files changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index b3c7eef53bf3..bf0b741d3243 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -534,6 +534,12 @@ transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) > return trans == TRANSCODER_EDP; > } > > +static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv) > +{ > + if (!dev_priv->psr.dc3co_exitline) > + return; > +} > + > static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > struct intel_crtc_state *crtc_state) > { > @@ -746,6 +752,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, > dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); > dev_priv->psr.busy_frontbuffer_bits = 0; > dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; > + dev_priv->psr.dc3co_exitline = crtc_state->dc3co_exitline; > dev_priv->psr.transcoder = crtc_state->cpu_transcoder; > > /* > @@ -829,6 +836,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv) > } > > if (dev_priv->psr.psr2_enabled) { > + tgl_disallow_dc3co_on_psr2_exit(dev_priv); > val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)); > WARN_ON(!(val & EDP_PSR2_ENABLE)); > val &= ~EDP_PSR2_ENABLE; > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index cddc98ea9965..c3aba078262f 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -501,6 +501,7 @@ struct i915_psr { > bool sink_not_reliable; > bool irq_aux_error; > u16 su_x_granularity; > + u32 dc3co_exitline; > }; > > #define QUIRK_LVDS_SSC_DISABLE (1<<1) > -- > 2.21.0 >
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b3c7eef53bf3..bf0b741d3243 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -534,6 +534,12 @@ transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) return trans == TRANSCODER_EDP; } +static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv) +{ + if (!dev_priv->psr.dc3co_exitline) + return; +} + static bool intel_psr2_config_valid(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { @@ -746,6 +752,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); dev_priv->psr.busy_frontbuffer_bits = 0; dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; + dev_priv->psr.dc3co_exitline = crtc_state->dc3co_exitline; dev_priv->psr.transcoder = crtc_state->cpu_transcoder; /* @@ -829,6 +836,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv) } if (dev_priv->psr.psr2_enabled) { + tgl_disallow_dc3co_on_psr2_exit(dev_priv); val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)); WARN_ON(!(val & EDP_PSR2_ENABLE)); val &= ~EDP_PSR2_ENABLE; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index cddc98ea9965..c3aba078262f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -501,6 +501,7 @@ struct i915_psr { bool sink_not_reliable; bool irq_aux_error; u16 su_x_granularity; + u32 dc3co_exitline; }; #define QUIRK_LVDS_SSC_DISABLE (1<<1)
Disallow DC3CO state before PSR2 exit. Store dc3co_exitline from crtc state to psr dev_priv structure to use it easily whenever it requires. v1: Moved calling of tgl_enable_psr2_transcoder_exitline() to intel_psr_enable(). [Imre] v2: Moved tgl_psr2_deep_sleep_enable/disable function to the patches where they are getting used and used dc3co_exitline check instead of TGL check. [Imre] Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++++++ drivers/gpu/drm/i915/i915_drv.h | 1 + 2 files changed, 9 insertions(+)