| Message ID | 20191001184141.27956-6-clabbe.montjoie@gmail.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Herbert Xu |
| Headers | show |
| Series | crypto: add sun8i-ce driver for Allwinner crypto engine | expand |
On Tue, Oct 01, 2019 at 08:41:35PM +0200, Corentin Labbe wrote: > The Crypto Engine is a hardware cryptographic accelerator that supports > many algorithms. > It could be found on most Allwinner SoCs. > > This patch enables the Crypto Engine on the Allwinner H3 SoC Device-tree. > > Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> > --- > arch/arm/boot/dts/sun8i-h3.dtsi | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi > index e37c30e811d3..778a23a794c9 100644 > --- a/arch/arm/boot/dts/sun8i-h3.dtsi > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > @@ -153,6 +153,17 @@ > allwinner,sram = <&ve_sram 1>; > }; > > + crypto: crypto@1c15000 { > + compatible = "allwinner,sun8i-h3-crypto"; > + reg = <0x01c15000 0x1000>; > + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "ce_ns"; That's not documented in the binding (and I guess unnecessary) > + resets = <&ccu RST_BUS_CE>; > + reset-names = "bus"; > + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; > + clock-names = "bus", "mod"; Nit: we put the clocks before the resets usually Maxime
On Wed, Oct 02, 2019 at 08:02:14AM +0200, Maxime Ripard wrote: > On Tue, Oct 01, 2019 at 08:41:35PM +0200, Corentin Labbe wrote: > > The Crypto Engine is a hardware cryptographic accelerator that supports > > many algorithms. > > It could be found on most Allwinner SoCs. > > > > This patch enables the Crypto Engine on the Allwinner H3 SoC Device-tree. > > > > Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> > > --- > > arch/arm/boot/dts/sun8i-h3.dtsi | 11 +++++++++++ > > 1 file changed, 11 insertions(+) > > > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi > > index e37c30e811d3..778a23a794c9 100644 > > --- a/arch/arm/boot/dts/sun8i-h3.dtsi > > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > > @@ -153,6 +153,17 @@ > > allwinner,sram = <&ve_sram 1>; > > }; > > > > + crypto: crypto@1c15000 { > > + compatible = "allwinner,sun8i-h3-crypto"; > > + reg = <0x01c15000 0x1000>; > > + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "ce_ns"; > > That's not documented in the binding (and I guess unnecessary) > Hello Yes this should be removed. > > + resets = <&ccu RST_BUS_CE>; > > + reset-names = "bus"; > > + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; > > + clock-names = "bus", "mod"; > > Nit: we put the clocks before the resets usually > Will do it. Thanks Regards
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index e37c30e811d3..778a23a794c9 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -153,6 +153,17 @@ allwinner,sram = <&ve_sram 1>; }; + crypto: crypto@1c15000 { + compatible = "allwinner,sun8i-h3-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ce_ns"; + resets = <&ccu RST_BUS_CE>; + reset-names = "bus"; + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; + clock-names = "bus", "mod"; + }; + mali: gpu@1c40000 { compatible = "allwinner,sun8i-h3-mali", "arm,mali-400"; reg = <0x01c40000 0x10000>;
The Crypto Engine is a hardware cryptographic accelerator that supports many algorithms. It could be found on most Allwinner SoCs. This patch enables the Crypto Engine on the Allwinner H3 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> --- arch/arm/boot/dts/sun8i-h3.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)