Message ID | alpine.DEB.2.21.9999.1910041036010.15827@viisi.sifive.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [GIT,PULL] RISC-V updates for v5.4-rc2 | expand |
On Fri, Oct 4, 2019 at 10:36 AM Paul Walmsley <paul.walmsley@sifive.com> wrote: > > - Ensure that exclusive-load reservations are terminated after system > call or exception handling. This primarily affects QEMU, which does > not expire load reservations. Grr. Can somebody talk sense to the RISC-V architects? Copying the PowerPC model was broken. PowerPC has now become the absolute worst architecture out there wrt just about any memory ordering issues, and the exclusive reservation is just another example of that. ARMv8 and even alpha got this right, and clear the reservation on return from traps/exceptions. Why did RISC-V copy the power model? (Yeah, I realize that ARM did too originally, but they learnt from their mistakes). Oh well. Linus
The pull request you sent on Fri, 4 Oct 2019 10:36:54 -0700 (PDT):
> git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv/for-v5.4-rc2
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/812ad49d88b51fab551acb3c2d9c7d054bc69423
Thank you!