| Message ID | 20190927222837.15758-1-radhakrishna.sripada@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | None | expand |
On Fri, Sep 27, 2019 at 03:28:37PM -0700, Radhakrishna Sripada wrote: > Render Decompression is supported with Y-Tiled main surface. The CCS is > linear and has 4 bits of data for each main surface cache line pair, a > ratio of 1:256. Additional Clear Color information is passed from the > user-space through an offset in the GEM BO. Add a new modifier to identify > and parse new Clear Color information and extend Gen12 render decompression > functionality to the newly added modifier. > > v2: Fix has_alpha flag for modifiers, omit CC modifier during initial > plane config(Matt). Fix Lookup error. > v3: Fix the panic while running kms_cube > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > Cc: Ville Syrjala <ville.syrjala@intel.com> > Cc: Shashank Sharma <shashank.sharma@intel.com> > Cc: Rafael Antognolli <rafael.antognolli@intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: Nanley G Chery <nanley.g.chery@intel.com> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 52 +++++++++++++++++++ > .../drm/i915/display/intel_display_types.h | 3 ++ > drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++- > drivers/gpu/drm/i915/i915_reg.h | 12 +++++ > 4 files changed, 77 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 4971c296f951..822237e98f00 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) > if (color_plane == 1) > return 64; > /* fall through */ > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > + if (color_plane == 1 || color_plane == 2) > + return 64; > + /* fall through */ > case I915_FORMAT_MOD_Y_TILED: > if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv)) > return 128; > @@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, > return 256 * 1024; > return 0; > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > return 16 * 1024; > case I915_FORMAT_MOD_Y_TILED_CCS: > case I915_FORMAT_MOD_Yf_TILED_CCS: > @@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int color_plane) > return true; > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > return color_plane == 1; > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > + return color_plane == 1 || color_plane == 2; > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > return color_plane == 1 || color_plane == 3; > default: > @@ -2458,6 +2465,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) > case I915_FORMAT_MOD_Y_TILED_CCS: > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > return I915_TILING_Y; > default: > return I915_TILING_NONE; > @@ -2511,6 +2519,25 @@ static const struct drm_format_info gen12_ccs_formats[] = { > .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true }, > }; > > +/* > + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the > + * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles > + * in the main surface. With 4 byte pixels and each Y-tile having dimensions of > + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels in > + * the main surface. Additional surface is used to pass the Clear Color > + * structure for the driver to program the DE. > + */ Rather than duplicating the previous comment's text I'd just say "Same as gen12_ccs_formats[] above, but with an additional surface used to pass..." > +static const struct drm_format_info gen12_ccs_cc_formats[] = { > + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3, > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, }, > + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3, > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, }, > + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3, > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true }, > + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3, > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true }, > +}; > + > static const struct drm_format_info * > lookup_format_info(const struct drm_format_info formats[], > int num_formats, u32 format) > @@ -2538,6 +2565,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) > return lookup_format_info(gen12_ccs_formats, > ARRAY_SIZE(gen12_ccs_formats), > cmd->pixel_format); > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > + return lookup_format_info(gen12_ccs_cc_formats, > + ARRAY_SIZE(gen12_ccs_cc_formats), > + cmd->pixel_format); > default: > return NULL; > } > @@ -2547,6 +2578,7 @@ bool is_ccs_modifier(u64 modifier) > { > return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || > modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || > + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC || > modifier == I915_FORMAT_MOD_Y_TILED_CCS || > modifier == I915_FORMAT_MOD_Yf_TILED_CCS; > } > @@ -2734,6 +2766,8 @@ static bool is_ccs_plane(u64 modifier, int color_plane) > return false; > else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) > return color_plane == 3 || color_plane == 1; > + else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) > + return color_plane == 1 || color_plane == 2; > else > return color_plane == 1; > } > @@ -2805,6 +2839,14 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, > cpp = fb->format->cpp[i]; > intel_fb_plane_dims(&width, &height, fb, i); > > + /* > + * Plane 2 of Render Compression with Clear Color fb modifier is consumed > + * by the driver and not passed to DE. Skip the arithmetic related to > + * alignment and offset calculation. > + */ > + if (i == 2 && fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) > + continue; > + We might as well do this before the cpp and width/height assignments too? Should we also be checking IS_ALIGNED(offsets[2], PAGE_SIZE)? We seem to rely on that after kmap'ing below. Matt > ret = intel_fb_offset_to_xy(&x, &y, fb, i); > if (ret) { > DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", > @@ -4274,6 +4316,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier) > case I915_FORMAT_MOD_Y_TILED: > return PLANE_CTL_TILED_Y; > case I915_FORMAT_MOD_Y_TILED_CCS: > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > return PLANE_CTL_TILED_Y | > @@ -14536,6 +14579,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state) > > plane_state->vma = vma; > > + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) { > + u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb), > + fb->offsets[2] >> PAGE_SHIFT)); > + > + plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32) > + | *(ccaddr + CC_VAL_LOWER_OFFSET); > + kunmap_atomic(ccaddr); > + } > + > return 0; > } > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 5998b959225c..77d3f6b634b0 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -579,6 +579,9 @@ struct intel_plane_state { > u32 planar_slave; > > struct drm_intel_sprite_colorkey ckey; > + > + /* Clear Color Value */ > + u64 ccval; > }; > > struct intel_initial_plane_config { > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c > index ce79373154fc..24ae8bf9744d 100644 > --- a/drivers/gpu/drm/i915/display/intel_sprite.c > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c > @@ -549,6 +549,7 @@ skl_program_plane(struct intel_plane *plane, > u32 plane_color_ctl = 0; > unsigned long irqflags; > u32 keymsk, keymax; > + u64 ccval = plane_state->ccval; > > plane_ctl |= skl_plane_ctl_crtc(crtc_state); > > @@ -609,6 +610,10 @@ skl_program_plane(struct intel_plane *plane, > if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) > icl_program_input_csc(plane, crtc_state, plane_state); > > + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) > + intel_uncore_write64_fw(&dev_priv->uncore, > + PLANE_CC_VAL(pipe, plane_id), ccval); > + > skl_write_plane_wm(plane, crtc_state); > > I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value); > @@ -1738,7 +1743,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, > fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || > fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS || > fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || > - fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) { > + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || > + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) { > DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n"); > return -EINVAL; > } > @@ -2153,6 +2159,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = { > static const u64 gen12_plane_format_modifiers_mc_ccs[] = { > I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, > + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, > I915_FORMAT_MOD_Y_TILED, > I915_FORMAT_MOD_X_TILED, > DRM_FORMAT_MOD_LINEAR, > @@ -2161,6 +2168,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = { > > static const u64 gen12_plane_format_modifiers_rc_ccs[] = { > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, > + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, > I915_FORMAT_MOD_Y_TILED, > I915_FORMAT_MOD_X_TILED, > DRM_FORMAT_MOD_LINEAR, > @@ -2334,6 +2342,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, > case I915_FORMAT_MOD_X_TILED: > case I915_FORMAT_MOD_Y_TILED: > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > break; > default: > return false; > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 0abf9a3917ed..01023fc880c8 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6734,6 +6734,8 @@ enum { > #define _PLANE_KEYMAX_1_A 0x701a0 > #define _PLANE_KEYMAX_2_A 0x702a0 > #define PLANE_KEYMAX_ALPHA(a) ((a) << 24) > +#define _PLANE_CC_VAL_1_A 0x701b4 > +#define _PLANE_CC_VAL_2_A 0x702b4 > #define _PLANE_AUX_DIST_1_A 0x701c0 > #define _PLANE_AUX_DIST_2_A 0x702c0 > #define _PLANE_AUX_OFFSET_1_A 0x701c4 > @@ -6773,6 +6775,16 @@ enum { > #define _PLANE_NV12_BUF_CFG_1_A 0x70278 > #define _PLANE_NV12_BUF_CFG_2_A 0x70378 > > +#define _PLANE_CC_VAL_1_B 0x711b4 > +#define _PLANE_CC_VAL_2_B 0x712b4 > +#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) > +#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) > +#define PLANE_CC_VAL(pipe, plane) \ > + _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe)) > + > +#define CC_VAL_LOWER_OFFSET 4 > +#define CC_VAL_HIGHER_OFFSET 5 > + > /* Input CSC Register Definitions */ > #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 > #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 > -- > 2.20.1 >
On Fri, 2019-10-04 at 16:52 -0700, Matt Roper wrote: > On Fri, Sep 27, 2019 at 03:28:37PM -0700, Radhakrishna Sripada wrote: > > Render Decompression is supported with Y-Tiled main surface. The CCS is > > linear and has 4 bits of data for each main surface cache line pair, a > > ratio of 1:256. Additional Clear Color information is passed from the > > user-space through an offset in the GEM BO. Add a new modifier to identify > > and parse new Clear Color information and extend Gen12 render decompression > > functionality to the newly added modifier. > > > > v2: Fix has_alpha flag for modifiers, omit CC modifier during initial > > plane config(Matt). Fix Lookup error. > > v3: Fix the panic while running kms_cube > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > Cc: Ville Syrjala <ville.syrjala@intel.com> > > Cc: Shashank Sharma <shashank.sharma@intel.com> > > Cc: Rafael Antognolli <rafael.antognolli@intel.com> > > Cc: Matt Roper <matthew.d.roper@intel.com> > > Cc: Nanley G Chery <nanley.g.chery@intel.com> > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 52 +++++++++++++++++++ > > .../drm/i915/display/intel_display_types.h | 3 ++ > > drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++- > > drivers/gpu/drm/i915/i915_reg.h | 12 +++++ > > 4 files changed, 77 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > b/drivers/gpu/drm/i915/display/intel_display.c > > index 4971c296f951..822237e98f00 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) > > if (color_plane == 1) > > return 64; > > /* fall through */ > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > + if (color_plane == 1 || color_plane == 2) > > + return 64; > > + /* fall through */ > > case I915_FORMAT_MOD_Y_TILED: > > if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv)) > > return 128; > > @@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, > > return 256 * 1024; > > return 0; > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > return 16 * 1024; > > case I915_FORMAT_MOD_Y_TILED_CCS: > > case I915_FORMAT_MOD_Yf_TILED_CCS: > > @@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int color_plane) > > return true; > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > > return color_plane == 1; > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > + return color_plane == 1 || color_plane == 2; > > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > > return color_plane == 1 || color_plane == 3; > > default: > > @@ -2458,6 +2465,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) > > case I915_FORMAT_MOD_Y_TILED_CCS: > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > return I915_TILING_Y; > > default: > > return I915_TILING_NONE; > > @@ -2511,6 +2519,25 @@ static const struct drm_format_info gen12_ccs_formats[] = { > > .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true }, > > }; > > > > +/* > > + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the > > + * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles > > + * in the main surface. With 4 byte pixels and each Y-tile having dimensions of > > + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels in > > + * the main surface. Additional surface is used to pass the Clear Color > > + * structure for the driver to program the DE. > > + */ > > Rather than duplicating the previous comment's text I'd just say > > "Same as gen12_ccs_formats[] above, but with an additional surface used > to pass..." > > > +static const struct drm_format_info gen12_ccs_cc_formats[] = { > > + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3, > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, }, > > + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3, > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, }, > > + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3, > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true }, > > + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3, > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true }, > > +}; > > + > > static const struct drm_format_info * > > lookup_format_info(const struct drm_format_info formats[], > > int num_formats, u32 format) > > @@ -2538,6 +2565,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) > > return lookup_format_info(gen12_ccs_formats, > > ARRAY_SIZE(gen12_ccs_formats), > > cmd->pixel_format); > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > + return lookup_format_info(gen12_ccs_cc_formats, > > + ARRAY_SIZE(gen12_ccs_cc_formats), > > + cmd->pixel_format); > > default: > > return NULL; > > } > > @@ -2547,6 +2578,7 @@ bool is_ccs_modifier(u64 modifier) > > { > > return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || > > modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || > > + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC || > > modifier == I915_FORMAT_MOD_Y_TILED_CCS || > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS; > > } > > @@ -2734,6 +2766,8 @@ static bool is_ccs_plane(u64 modifier, int color_plane) > > return false; > > else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) > > return color_plane == 3 || color_plane == 1; > > + else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) > > + return color_plane == 1 || color_plane == 2; > > else > > return color_plane == 1; > > } > > @@ -2805,6 +2839,14 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, > > cpp = fb->format->cpp[i]; > > intel_fb_plane_dims(&width, &height, fb, i); > > > > + /* > > + * Plane 2 of Render Compression with Clear Color fb modifier is consumed > > + * by the driver and not passed to DE. Skip the arithmetic related to > > + * alignment and offset calculation. > > + */ > > + if (i == 2 && fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) > > + continue; > > + > > We might as well do this before the cpp and width/height assignments too? > > Should we also be checking IS_ALIGNED(offsets[2], PAGE_SIZE)? We seem > to rely on that after kmap'ing below. I am wondering if it needs to be page aligned. Since Clear Color data follows a linear CCS, would a 64B alignment suffice? -DK > > > Matt > > > ret = intel_fb_offset_to_xy(&x, &y, fb, i); > > if (ret) { > > DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", > > @@ -4274,6 +4316,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier) > > case I915_FORMAT_MOD_Y_TILED: > > return PLANE_CTL_TILED_Y; > > case I915_FORMAT_MOD_Y_TILED_CCS: > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > > return PLANE_CTL_TILED_Y | > > @@ -14536,6 +14579,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state) > > > > plane_state->vma = vma; > > > > + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) { > > + u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb), > > + fb->offsets[2] >> PAGE_SHIFT)); > > + > > + plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32) > > + | *(ccaddr + CC_VAL_LOWER_OFFSET); > > + kunmap_atomic(ccaddr); > > + } > > + > > return 0; > > } > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > index 5998b959225c..77d3f6b634b0 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > @@ -579,6 +579,9 @@ struct intel_plane_state { > > u32 planar_slave; > > > > struct drm_intel_sprite_colorkey ckey; > > + > > + /* Clear Color Value */ > > + u64 ccval; > > }; > > > > struct intel_initial_plane_config { > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c > > b/drivers/gpu/drm/i915/display/intel_sprite.c > > index ce79373154fc..24ae8bf9744d 100644 > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c > > @@ -549,6 +549,7 @@ skl_program_plane(struct intel_plane *plane, > > u32 plane_color_ctl = 0; > > unsigned long irqflags; > > u32 keymsk, keymax; > > + u64 ccval = plane_state->ccval; > > > > plane_ctl |= skl_plane_ctl_crtc(crtc_state); > > > > @@ -609,6 +610,10 @@ skl_program_plane(struct intel_plane *plane, > > if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) > > icl_program_input_csc(plane, crtc_state, plane_state); > > > > + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) > > + intel_uncore_write64_fw(&dev_priv->uncore, > > + PLANE_CC_VAL(pipe, plane_id), ccval); > > + > > skl_write_plane_wm(plane, crtc_state); > > > > I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value); > > @@ -1738,7 +1743,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, > > fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || > > fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS || > > fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || > > - fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) { > > + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || > > + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) { > > DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n"); > > return -EINVAL; > > } > > @@ -2153,6 +2159,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = { > > static const u64 gen12_plane_format_modifiers_mc_ccs[] = { > > I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, > > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, > > + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, > > I915_FORMAT_MOD_Y_TILED, > > I915_FORMAT_MOD_X_TILED, > > DRM_FORMAT_MOD_LINEAR, > > @@ -2161,6 +2168,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = { > > > > static const u64 gen12_plane_format_modifiers_rc_ccs[] = { > > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, > > + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, > > I915_FORMAT_MOD_Y_TILED, > > I915_FORMAT_MOD_X_TILED, > > DRM_FORMAT_MOD_LINEAR, > > @@ -2334,6 +2342,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, > > case I915_FORMAT_MOD_X_TILED: > > case I915_FORMAT_MOD_Y_TILED: > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > break; > > default: > > return false; > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 0abf9a3917ed..01023fc880c8 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -6734,6 +6734,8 @@ enum { > > #define _PLANE_KEYMAX_1_A 0x701a0 > > #define _PLANE_KEYMAX_2_A 0x702a0 > > #define PLANE_KEYMAX_ALPHA(a) ((a) << 24) > > +#define _PLANE_CC_VAL_1_A 0x701b4 > > +#define _PLANE_CC_VAL_2_A 0x702b4 > > #define _PLANE_AUX_DIST_1_A 0x701c0 > > #define _PLANE_AUX_DIST_2_A 0x702c0 > > #define _PLANE_AUX_OFFSET_1_A 0x701c4 > > @@ -6773,6 +6775,16 @@ enum { > > #define _PLANE_NV12_BUF_CFG_1_A 0x70278 > > #define _PLANE_NV12_BUF_CFG_2_A 0x70378 > > > > +#define _PLANE_CC_VAL_1_B 0x711b4 > > +#define _PLANE_CC_VAL_2_B 0x712b4 > > +#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) > > +#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) > > +#define PLANE_CC_VAL(pipe, plane) \ > > + _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe)) > > + > > +#define CC_VAL_LOWER_OFFSET 4 > > +#define CC_VAL_HIGHER_OFFSET 5 > > + > > /* Input CSC Register Definitions */ > > #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 > > #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 > > -- > > 2.20.1 > > > >
On Fri, Oct 04, 2019 at 05:17:07PM -0700, Dhinakaran Pandiyan wrote: > On Fri, 2019-10-04 at 16:52 -0700, Matt Roper wrote: > > On Fri, Sep 27, 2019 at 03:28:37PM -0700, Radhakrishna Sripada wrote: > > > Render Decompression is supported with Y-Tiled main surface. The CCS is > > > linear and has 4 bits of data for each main surface cache line pair, a > > > ratio of 1:256. Additional Clear Color information is passed from the > > > user-space through an offset in the GEM BO. Add a new modifier to identify > > > and parse new Clear Color information and extend Gen12 render decompression > > > functionality to the newly added modifier. > > > > > > v2: Fix has_alpha flag for modifiers, omit CC modifier during initial > > > plane config(Matt). Fix Lookup error. > > > v3: Fix the panic while running kms_cube > > > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > > Cc: Ville Syrjala <ville.syrjala@intel.com> > > > Cc: Shashank Sharma <shashank.sharma@intel.com> > > > Cc: Rafael Antognolli <rafael.antognolli@intel.com> > > > Cc: Matt Roper <matthew.d.roper@intel.com> > > > Cc: Nanley G Chery <nanley.g.chery@intel.com> > > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_display.c | 52 +++++++++++++++++++ > > > .../drm/i915/display/intel_display_types.h | 3 ++ > > > drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++- > > > drivers/gpu/drm/i915/i915_reg.h | 12 +++++ > > > 4 files changed, 77 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > > b/drivers/gpu/drm/i915/display/intel_display.c > > > index 4971c296f951..822237e98f00 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) > > > if (color_plane == 1) > > > return 64; > > > /* fall through */ > > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > > + if (color_plane == 1 || color_plane == 2) > > > + return 64; > > > + /* fall through */ > > > case I915_FORMAT_MOD_Y_TILED: > > > if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv)) > > > return 128; > > > @@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, > > > return 256 * 1024; > > > return 0; > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > > return 16 * 1024; > > > case I915_FORMAT_MOD_Y_TILED_CCS: > > > case I915_FORMAT_MOD_Yf_TILED_CCS: > > > @@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int color_plane) > > > return true; > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > > > return color_plane == 1; > > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > > + return color_plane == 1 || color_plane == 2; > > > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > > > return color_plane == 1 || color_plane == 3; > > > default: > > > @@ -2458,6 +2465,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) > > > case I915_FORMAT_MOD_Y_TILED_CCS: > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > > > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > > return I915_TILING_Y; > > > default: > > > return I915_TILING_NONE; > > > @@ -2511,6 +2519,25 @@ static const struct drm_format_info gen12_ccs_formats[] = { > > > .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true }, > > > }; > > > > > > +/* > > > + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the > > > + * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles > > > + * in the main surface. With 4 byte pixels and each Y-tile having dimensions of > > > + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels in > > > + * the main surface. Additional surface is used to pass the Clear Color > > > + * structure for the driver to program the DE. > > > + */ > > > > Rather than duplicating the previous comment's text I'd just say > > > > "Same as gen12_ccs_formats[] above, but with an additional surface used > > to pass..." > > > > > +static const struct drm_format_info gen12_ccs_cc_formats[] = { > > > + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3, > > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, }, > > > + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3, > > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, }, > > > + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3, > > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true }, > > > + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3, > > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true }, > > > +}; > > > + > > > static const struct drm_format_info * > > > lookup_format_info(const struct drm_format_info formats[], > > > int num_formats, u32 format) > > > @@ -2538,6 +2565,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) > > > return lookup_format_info(gen12_ccs_formats, > > > ARRAY_SIZE(gen12_ccs_formats), > > > cmd->pixel_format); > > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > > + return lookup_format_info(gen12_ccs_cc_formats, > > > + ARRAY_SIZE(gen12_ccs_cc_formats), > > > + cmd->pixel_format); > > > default: > > > return NULL; > > > } > > > @@ -2547,6 +2578,7 @@ bool is_ccs_modifier(u64 modifier) > > > { > > > return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || > > > modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || > > > + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC || > > > modifier == I915_FORMAT_MOD_Y_TILED_CCS || > > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS; > > > } > > > @@ -2734,6 +2766,8 @@ static bool is_ccs_plane(u64 modifier, int color_plane) > > > return false; > > > else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) > > > return color_plane == 3 || color_plane == 1; > > > + else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) > > > + return color_plane == 1 || color_plane == 2; > > > else > > > return color_plane == 1; > > > } > > > @@ -2805,6 +2839,14 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, > > > cpp = fb->format->cpp[i]; > > > intel_fb_plane_dims(&width, &height, fb, i); > > > > > > + /* > > > + * Plane 2 of Render Compression with Clear Color fb modifier is consumed > > > + * by the driver and not passed to DE. Skip the arithmetic related to > > > + * alignment and offset calculation. > > > + */ > > > + if (i == 2 && fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) > > > + continue; > > > + > > > > We might as well do this before the cpp and width/height assignments too? > > > > Should we also be checking IS_ALIGNED(offsets[2], PAGE_SIZE)? We seem > > to rely on that after kmap'ing below. > > I am wondering if it needs to be page aligned. Since Clear Color data follows a linear CCS, would a > 64B alignment suffice? > > -DK The kmap_atomic() farther down gives you a pointer to the beginning of the page that holds the CC. So if you don't require page alignment, you'll just need to account for that when extracting ccval below. Matt > > > > > > > Matt > > > > > ret = intel_fb_offset_to_xy(&x, &y, fb, i); > > > if (ret) { > > > DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", > > > @@ -4274,6 +4316,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier) > > > case I915_FORMAT_MOD_Y_TILED: > > > return PLANE_CTL_TILED_Y; > > > case I915_FORMAT_MOD_Y_TILED_CCS: > > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > > > return PLANE_CTL_TILED_Y | > > > @@ -14536,6 +14579,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state) > > > > > > plane_state->vma = vma; > > > > > > + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) { > > > + u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb), > > > + fb->offsets[2] >> PAGE_SHIFT)); > > > + > > > + plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32) > > > + | *(ccaddr + CC_VAL_LOWER_OFFSET); > > > + kunmap_atomic(ccaddr); > > > + } > > > + > > > return 0; > > > } > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > > index 5998b959225c..77d3f6b634b0 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > > @@ -579,6 +579,9 @@ struct intel_plane_state { > > > u32 planar_slave; > > > > > > struct drm_intel_sprite_colorkey ckey; > > > + > > > + /* Clear Color Value */ > > > + u64 ccval; > > > }; > > > > > > struct intel_initial_plane_config { > > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c > > > b/drivers/gpu/drm/i915/display/intel_sprite.c > > > index ce79373154fc..24ae8bf9744d 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c > > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c > > > @@ -549,6 +549,7 @@ skl_program_plane(struct intel_plane *plane, > > > u32 plane_color_ctl = 0; > > > unsigned long irqflags; > > > u32 keymsk, keymax; > > > + u64 ccval = plane_state->ccval; > > > > > > plane_ctl |= skl_plane_ctl_crtc(crtc_state); > > > > > > @@ -609,6 +610,10 @@ skl_program_plane(struct intel_plane *plane, > > > if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) > > > icl_program_input_csc(plane, crtc_state, plane_state); > > > > > > + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) > > > + intel_uncore_write64_fw(&dev_priv->uncore, > > > + PLANE_CC_VAL(pipe, plane_id), ccval); > > > + > > > skl_write_plane_wm(plane, crtc_state); > > > > > > I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value); > > > @@ -1738,7 +1743,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, > > > fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || > > > fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS || > > > fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || > > > - fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) { > > > + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || > > > + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) { > > > DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n"); > > > return -EINVAL; > > > } > > > @@ -2153,6 +2159,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = { > > > static const u64 gen12_plane_format_modifiers_mc_ccs[] = { > > > I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, > > > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, > > > + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, > > > I915_FORMAT_MOD_Y_TILED, > > > I915_FORMAT_MOD_X_TILED, > > > DRM_FORMAT_MOD_LINEAR, > > > @@ -2161,6 +2168,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = { > > > > > > static const u64 gen12_plane_format_modifiers_rc_ccs[] = { > > > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, > > > + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, > > > I915_FORMAT_MOD_Y_TILED, > > > I915_FORMAT_MOD_X_TILED, > > > DRM_FORMAT_MOD_LINEAR, > > > @@ -2334,6 +2342,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, > > > case I915_FORMAT_MOD_X_TILED: > > > case I915_FORMAT_MOD_Y_TILED: > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > > break; > > > default: > > > return false; > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > > index 0abf9a3917ed..01023fc880c8 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -6734,6 +6734,8 @@ enum { > > > #define _PLANE_KEYMAX_1_A 0x701a0 > > > #define _PLANE_KEYMAX_2_A 0x702a0 > > > #define PLANE_KEYMAX_ALPHA(a) ((a) << 24) > > > +#define _PLANE_CC_VAL_1_A 0x701b4 > > > +#define _PLANE_CC_VAL_2_A 0x702b4 > > > #define _PLANE_AUX_DIST_1_A 0x701c0 > > > #define _PLANE_AUX_DIST_2_A 0x702c0 > > > #define _PLANE_AUX_OFFSET_1_A 0x701c4 > > > @@ -6773,6 +6775,16 @@ enum { > > > #define _PLANE_NV12_BUF_CFG_1_A 0x70278 > > > #define _PLANE_NV12_BUF_CFG_2_A 0x70378 > > > > > > +#define _PLANE_CC_VAL_1_B 0x711b4 > > > +#define _PLANE_CC_VAL_2_B 0x712b4 > > > +#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) > > > +#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) > > > +#define PLANE_CC_VAL(pipe, plane) \ > > > + _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe)) > > > + > > > +#define CC_VAL_LOWER_OFFSET 4 > > > +#define CC_VAL_HIGHER_OFFSET 5 > > > + > > > /* Input CSC Register Definitions */ > > > #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 > > > #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 > > > -- > > > 2.20.1 > > > > > > > >
Hi Matt, > -----Original Message----- > From: Roper, Matthew D > Sent: Friday, October 4, 2019 4:53 PM > To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran > <dhinakaran.pandiyan@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>; > Sharma, Shashank <shashank.sharma@intel.com>; Antognolli, Rafael > <rafael.antognolli@intel.com>; Chery, Nanley G <nanley.g.chery@intel.com> > Subject: Re: [PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL > Render Decompression > > On Fri, Sep 27, 2019 at 03:28:37PM -0700, Radhakrishna Sripada wrote: > > Render Decompression is supported with Y-Tiled main surface. The CCS > > is linear and has 4 bits of data for each main surface cache line > > pair, a ratio of 1:256. Additional Clear Color information is passed > > from the user-space through an offset in the GEM BO. Add a new > > modifier to identify and parse new Clear Color information and extend > > Gen12 render decompression functionality to the newly added modifier. > > > > v2: Fix has_alpha flag for modifiers, omit CC modifier during initial > > plane config(Matt). Fix Lookup error. > > v3: Fix the panic while running kms_cube > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > Cc: Ville Syrjala <ville.syrjala@intel.com> > > Cc: Shashank Sharma <shashank.sharma@intel.com> > > Cc: Rafael Antognolli <rafael.antognolli@intel.com> > > Cc: Matt Roper <matthew.d.roper@intel.com> > > Cc: Nanley G Chery <nanley.g.chery@intel.com> > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 52 +++++++++++++++++++ > > .../drm/i915/display/intel_display_types.h | 3 ++ > > drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++- > > drivers/gpu/drm/i915/i915_reg.h | 12 +++++ > > 4 files changed, 77 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > b/drivers/gpu/drm/i915/display/intel_display.c > > index 4971c296f951..822237e98f00 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct > drm_framebuffer *fb, int color_plane) > > if (color_plane == 1) > > return 64; > > /* fall through */ > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > + if (color_plane == 1 || color_plane == 2) > > + return 64; > > + /* fall through */ > > case I915_FORMAT_MOD_Y_TILED: > > if (IS_GEN(dev_priv, 2) || > HAS_128_BYTE_Y_TILING(dev_priv)) > > return 128; > > @@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const > struct drm_framebuffer *fb, > > return 256 * 1024; > > return 0; > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > return 16 * 1024; > > case I915_FORMAT_MOD_Y_TILED_CCS: > > case I915_FORMAT_MOD_Yf_TILED_CCS: > > @@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int > color_plane) > > return true; > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > > return color_plane == 1; > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > + return color_plane == 1 || color_plane == 2; > > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > > return color_plane == 1 || color_plane == 3; > > default: > > @@ -2458,6 +2465,7 @@ static unsigned int > intel_fb_modifier_to_tiling(u64 fb_modifier) > > case I915_FORMAT_MOD_Y_TILED_CCS: > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > return I915_TILING_Y; > > default: > > return I915_TILING_NONE; > > @@ -2511,6 +2519,25 @@ static const struct drm_format_info > gen12_ccs_formats[] = { > > .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true }, }; > > > > +/* > > + * Gen-12 compression uses 4 bits of CCS data for each cache line > > +pair in the > > + * main surface. And each 64B CCS cache line represents an area of > > +4x1 Y-tiles > > + * in the main surface. With 4 byte pixels and each Y-tile having > > +dimensions of > > + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x > > +32 pixels in > > + * the main surface. Additional surface is used to pass the Clear > > +Color > > + * structure for the driver to program the DE. > > + */ > > Rather than duplicating the previous comment's text I'd just say > > "Same as gen12_ccs_formats[] above, but with an additional surface used to > pass..." Sure will update that in the next rev. > > > +static const struct drm_format_info gen12_ccs_cc_formats[] = { > > + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3, > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, }, > > + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3, > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, }, > > + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3, > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true }, > > + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3, > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true }, > > +}; > > + > > static const struct drm_format_info * lookup_format_info(const > > struct drm_format_info formats[], > > int num_formats, u32 format) > > @@ -2538,6 +2565,10 @@ intel_get_format_info(const struct > drm_mode_fb_cmd2 *cmd) > > return lookup_format_info(gen12_ccs_formats, > > ARRAY_SIZE(gen12_ccs_formats), > > cmd->pixel_format); > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > + return lookup_format_info(gen12_ccs_cc_formats, > > + ARRAY_SIZE(gen12_ccs_cc_formats), > > + cmd->pixel_format); > > default: > > return NULL; > > } > > @@ -2547,6 +2578,7 @@ bool is_ccs_modifier(u64 modifier) { > > return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || > > modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || > > + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC || > > modifier == I915_FORMAT_MOD_Y_TILED_CCS || > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS; } @@ -2734,6 > > +2766,8 @@ static bool is_ccs_plane(u64 modifier, int color_plane) > > return false; > > else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) > > return color_plane == 3 || color_plane == 1; > > + else if (modifier == > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) > > + return color_plane == 1 || color_plane == 2; > > else > > return color_plane == 1; > > } > > @@ -2805,6 +2839,14 @@ intel_fill_fb_info(struct drm_i915_private > *dev_priv, > > cpp = fb->format->cpp[i]; > > intel_fb_plane_dims(&width, &height, fb, i); > > > > + /* > > + * Plane 2 of Render Compression with Clear Color fb > modifier is consumed > > + * by the driver and not passed to DE. Skip the arithmetic > related to > > + * alignment and offset calculation. > > + */ > > + if (i == 2 && fb->modifier == > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) > > + continue; > > + > > We might as well do this before the cpp and width/height assignments too? > > Should we also be checking IS_ALIGNED(offsets[2], PAGE_SIZE)? We seem to > rely on that after kmap'ing below. Will make the changes in next rev. Thanks, Radhakrishna(RK) Sripada > > > Matt > > > ret = intel_fb_offset_to_xy(&x, &y, fb, i); > > if (ret) { > > DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", > @@ -4274,6 +4316,7 > > @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier) > > case I915_FORMAT_MOD_Y_TILED: > > return PLANE_CTL_TILED_Y; > > case I915_FORMAT_MOD_Y_TILED_CCS: > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > return PLANE_CTL_TILED_Y | > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > > return PLANE_CTL_TILED_Y | > > @@ -14536,6 +14579,15 @@ static int intel_plane_pin_fb(struct > > intel_plane_state *plane_state) > > > > plane_state->vma = vma; > > > > + if (fb->modifier == > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) { > > + u32 *ccaddr = > kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb), > > + fb- > >offsets[2] >> PAGE_SHIFT)); > > + > > + plane_state->ccval = ((u64)*(ccaddr + > CC_VAL_HIGHER_OFFSET) << 32) > > + | *(ccaddr + CC_VAL_LOWER_OFFSET); > > + kunmap_atomic(ccaddr); > > + } > > + > > return 0; > > } > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > index 5998b959225c..77d3f6b634b0 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > @@ -579,6 +579,9 @@ struct intel_plane_state { > > u32 planar_slave; > > > > struct drm_intel_sprite_colorkey ckey; > > + > > + /* Clear Color Value */ > > + u64 ccval; > > }; > > > > struct intel_initial_plane_config { > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c > > b/drivers/gpu/drm/i915/display/intel_sprite.c > > index ce79373154fc..24ae8bf9744d 100644 > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c > > @@ -549,6 +549,7 @@ skl_program_plane(struct intel_plane *plane, > > u32 plane_color_ctl = 0; > > unsigned long irqflags; > > u32 keymsk, keymax; > > + u64 ccval = plane_state->ccval; > > > > plane_ctl |= skl_plane_ctl_crtc(crtc_state); > > > > @@ -609,6 +610,10 @@ skl_program_plane(struct intel_plane *plane, > > if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) > > icl_program_input_csc(plane, crtc_state, plane_state); > > > > + if (fb->modifier == > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) > > + intel_uncore_write64_fw(&dev_priv->uncore, > > + PLANE_CC_VAL(pipe, plane_id), > ccval); > > + > > skl_write_plane_wm(plane, crtc_state); > > > > I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value); > @@ > > -1738,7 +1743,8 @@ static int skl_plane_check_fb(const struct > intel_crtc_state *crtc_state, > > fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || > > fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS || > > fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || > > - fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) { > > + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || > > + fb->modifier == > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) { > > DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID > mode\n"); > > return -EINVAL; > > } > > @@ -2153,6 +2159,7 @@ static const u64 > > skl_plane_format_modifiers_ccs[] = { static const u64 > gen12_plane_format_modifiers_mc_ccs[] = { > > I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, > > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, > > + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, > > I915_FORMAT_MOD_Y_TILED, > > I915_FORMAT_MOD_X_TILED, > > DRM_FORMAT_MOD_LINEAR, > > @@ -2161,6 +2168,7 @@ static const u64 > > gen12_plane_format_modifiers_mc_ccs[] = { > > > > static const u64 gen12_plane_format_modifiers_rc_ccs[] = { > > I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, > > + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, > > I915_FORMAT_MOD_Y_TILED, > > I915_FORMAT_MOD_X_TILED, > > DRM_FORMAT_MOD_LINEAR, > > @@ -2334,6 +2342,7 @@ static bool > gen12_plane_format_mod_supported(struct drm_plane *_plane, > > case I915_FORMAT_MOD_X_TILED: > > case I915_FORMAT_MOD_Y_TILED: > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > break; > > default: > > return false; > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h index 0abf9a3917ed..01023fc880c8 > > 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -6734,6 +6734,8 @@ enum { > > #define _PLANE_KEYMAX_1_A 0x701a0 > > #define _PLANE_KEYMAX_2_A 0x702a0 > > #define PLANE_KEYMAX_ALPHA(a) ((a) << 24) > > +#define _PLANE_CC_VAL_1_A 0x701b4 > > +#define _PLANE_CC_VAL_2_A 0x702b4 > > #define _PLANE_AUX_DIST_1_A 0x701c0 > > #define _PLANE_AUX_DIST_2_A 0x702c0 > > #define _PLANE_AUX_OFFSET_1_A 0x701c4 > > @@ -6773,6 +6775,16 @@ enum { > > #define _PLANE_NV12_BUF_CFG_1_A 0x70278 > > #define _PLANE_NV12_BUF_CFG_2_A 0x70378 > > > > +#define _PLANE_CC_VAL_1_B 0x711b4 > > +#define _PLANE_CC_VAL_2_B 0x712b4 > > +#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A, > _PLANE_CC_VAL_1_B) > > +#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A, > _PLANE_CC_VAL_2_B) > > +#define PLANE_CC_VAL(pipe, plane) \ > > + _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), > _PLANE_CC_VAL_2(pipe)) > > + > > +#define CC_VAL_LOWER_OFFSET 4 > > +#define CC_VAL_HIGHER_OFFSET 5 > > + > > /* Input CSC Register Definitions */ > > #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 > > #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 > > -- > > 2.20.1 > > > > -- > Matt Roper > Graphics Software Engineer > VTT-OSGC Platform Enablement > Intel Corporation > (916) 356-2795
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 4971c296f951..822237e98f00 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) if (color_plane == 1) return 64; /* fall through */ + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: + if (color_plane == 1 || color_plane == 2) + return 64; + /* fall through */ case I915_FORMAT_MOD_Y_TILED: if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv)) return 128; @@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, return 256 * 1024; return 0; case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: return 16 * 1024; case I915_FORMAT_MOD_Y_TILED_CCS: case I915_FORMAT_MOD_Yf_TILED_CCS: @@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int color_plane) return true; case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: return color_plane == 1; + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: + return color_plane == 1 || color_plane == 2; case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: return color_plane == 1 || color_plane == 3; default: @@ -2458,6 +2465,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) case I915_FORMAT_MOD_Y_TILED_CCS: case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: return I915_TILING_Y; default: return I915_TILING_NONE; @@ -2511,6 +2519,25 @@ static const struct drm_format_info gen12_ccs_formats[] = { .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true }, }; +/* + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the + * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles + * in the main surface. With 4 byte pixels and each Y-tile having dimensions of + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels in + * the main surface. Additional surface is used to pass the Clear Color + * structure for the driver to program the DE. + */ +static const struct drm_format_info gen12_ccs_cc_formats[] = { + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3, + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, }, + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3, + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, }, + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3, + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true }, + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3, + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true }, +}; + static const struct drm_format_info * lookup_format_info(const struct drm_format_info formats[], int num_formats, u32 format) @@ -2538,6 +2565,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) return lookup_format_info(gen12_ccs_formats, ARRAY_SIZE(gen12_ccs_formats), cmd->pixel_format); + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: + return lookup_format_info(gen12_ccs_cc_formats, + ARRAY_SIZE(gen12_ccs_cc_formats), + cmd->pixel_format); default: return NULL; } @@ -2547,6 +2578,7 @@ bool is_ccs_modifier(u64 modifier) { return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC || modifier == I915_FORMAT_MOD_Y_TILED_CCS || modifier == I915_FORMAT_MOD_Yf_TILED_CCS; } @@ -2734,6 +2766,8 @@ static bool is_ccs_plane(u64 modifier, int color_plane) return false; else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) return color_plane == 3 || color_plane == 1; + else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) + return color_plane == 1 || color_plane == 2; else return color_plane == 1; } @@ -2805,6 +2839,14 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, cpp = fb->format->cpp[i]; intel_fb_plane_dims(&width, &height, fb, i); + /* + * Plane 2 of Render Compression with Clear Color fb modifier is consumed + * by the driver and not passed to DE. Skip the arithmetic related to + * alignment and offset calculation. + */ + if (i == 2 && fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) + continue; + ret = intel_fb_offset_to_xy(&x, &y, fb, i); if (ret) { DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", @@ -4274,6 +4316,7 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier) case I915_FORMAT_MOD_Y_TILED: return PLANE_CTL_TILED_Y; case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: return PLANE_CTL_TILED_Y | @@ -14536,6 +14579,15 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state) plane_state->vma = vma; + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) { + u32 *ccaddr = kmap_atomic(i915_gem_object_get_page(intel_fb_obj(fb), + fb->offsets[2] >> PAGE_SHIFT)); + + plane_state->ccval = ((u64)*(ccaddr + CC_VAL_HIGHER_OFFSET) << 32) + | *(ccaddr + CC_VAL_LOWER_OFFSET); + kunmap_atomic(ccaddr); + } + return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 5998b959225c..77d3f6b634b0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -579,6 +579,9 @@ struct intel_plane_state { u32 planar_slave; struct drm_intel_sprite_colorkey ckey; + + /* Clear Color Value */ + u64 ccval; }; struct intel_initial_plane_config { diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index ce79373154fc..24ae8bf9744d 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -549,6 +549,7 @@ skl_program_plane(struct intel_plane *plane, u32 plane_color_ctl = 0; unsigned long irqflags; u32 keymsk, keymax; + u64 ccval = plane_state->ccval; plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -609,6 +610,10 @@ skl_program_plane(struct intel_plane *plane, if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) icl_program_input_csc(plane, crtc_state, plane_state); + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) + intel_uncore_write64_fw(&dev_priv->uncore, + PLANE_CC_VAL(pipe, plane_id), ccval); + skl_write_plane_wm(plane, crtc_state); I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value); @@ -1738,7 +1743,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS || fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || - fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) { + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) { DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n"); return -EINVAL; } @@ -2153,6 +2159,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = { static const u64 gen12_plane_format_modifiers_mc_ccs[] = { I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED, DRM_FORMAT_MOD_LINEAR, @@ -2161,6 +2168,7 @@ static const u64 gen12_plane_format_modifiers_mc_ccs[] = { static const u64 gen12_plane_format_modifiers_rc_ccs[] = { I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED, DRM_FORMAT_MOD_LINEAR, @@ -2334,6 +2342,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, case I915_FORMAT_MOD_X_TILED: case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: break; default: return false; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0abf9a3917ed..01023fc880c8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6734,6 +6734,8 @@ enum { #define _PLANE_KEYMAX_1_A 0x701a0 #define _PLANE_KEYMAX_2_A 0x702a0 #define PLANE_KEYMAX_ALPHA(a) ((a) << 24) +#define _PLANE_CC_VAL_1_A 0x701b4 +#define _PLANE_CC_VAL_2_A 0x702b4 #define _PLANE_AUX_DIST_1_A 0x701c0 #define _PLANE_AUX_DIST_2_A 0x702c0 #define _PLANE_AUX_OFFSET_1_A 0x701c4 @@ -6773,6 +6775,16 @@ enum { #define _PLANE_NV12_BUF_CFG_1_A 0x70278 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 +#define _PLANE_CC_VAL_1_B 0x711b4 +#define _PLANE_CC_VAL_2_B 0x712b4 +#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) +#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) +#define PLANE_CC_VAL(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe)) + +#define CC_VAL_LOWER_OFFSET 4 +#define CC_VAL_HIGHER_OFFSET 5 + /* Input CSC Register Definitions */ #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
Render Decompression is supported with Y-Tiled main surface. The CCS is linear and has 4 bits of data for each main surface cache line pair, a ratio of 1:256. Additional Clear Color information is passed from the user-space through an offset in the GEM BO. Add a new modifier to identify and parse new Clear Color information and extend Gen12 render decompression functionality to the newly added modifier. v2: Fix has_alpha flag for modifiers, omit CC modifier during initial plane config(Matt). Fix Lookup error. v3: Fix the panic while running kms_cube Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Ville Syrjala <ville.syrjala@intel.com> Cc: Shashank Sharma <shashank.sharma@intel.com> Cc: Rafael Antognolli <rafael.antognolli@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Nanley G Chery <nanley.g.chery@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 52 +++++++++++++++++++ .../drm/i915/display/intel_display_types.h | 3 ++ drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++- drivers/gpu/drm/i915/i915_reg.h | 12 +++++ 4 files changed, 77 insertions(+), 1 deletion(-)