[0/2] iommu/arm-smmu: Add an optional "input-address-size" property

Message

Nicolin Chen Oct. 11, 2019, 3:46 a.m. UTC

This series of patches add an optional DT property to allow an SoC to
specify how many bits being physically connected to its SMMU instance,
depending on the SoC design.

Nicolin Chen (2):
  dt-bindings: arm-smmu: Add an optional "input-address-size" property
  iommu/arm-smmu: Read optional "input-address-size" property

 Documentation/devicetree/bindings/iommu/arm,smmu.txt |  7 +++++++
 drivers/iommu/arm-smmu.c                             | 10 ++++++++--
 2 files changed, 15 insertions(+), 2 deletions(-)

Comments

Robin Murphy Oct. 11, 2019, 9:16 a.m. UTC | #1

On 2019-10-11 4:46 am, Nicolin Chen wrote:
> This series of patches add an optional DT property to allow an SoC to
> specify how many bits being physically connected to its SMMU instance,
> depending on the SoC design.

This has come up before, and it doesn't work in general because a single 
SMMU instance can have many master interfaces, with potentially 
different sizes of address bus wired up to each. It's also a 
conceptually-wrong approach anyway, since this isn't a property of the 
SMMU; it's a property of the interconnect(s) upstream of the SMMU.

IIRC you were working on Tegra - if so, Thierry already has a plan, see 
this thread: 
https://lore.kernel.org/linux-arm-kernel/20190930133510.GA1904140@ulmo/

Robin.

> 
> Nicolin Chen (2):
>    dt-bindings: arm-smmu: Add an optional "input-address-size" property
>    iommu/arm-smmu: Read optional "input-address-size" property
> 
>   Documentation/devicetree/bindings/iommu/arm,smmu.txt |  7 +++++++
>   drivers/iommu/arm-smmu.c                             | 10 ++++++++--
>   2 files changed, 15 insertions(+), 2 deletions(-)
>

Nicolin Chen Oct. 11, 2019, 11:55 p.m. UTC | #2

On Fri, Oct 11, 2019 at 10:16:28AM +0100, Robin Murphy wrote:
> On 2019-10-11 4:46 am, Nicolin Chen wrote:
> > This series of patches add an optional DT property to allow an SoC to
> > specify how many bits being physically connected to its SMMU instance,
> > depending on the SoC design.
> 
> This has come up before, and it doesn't work in general because a single
> SMMU instance can have many master interfaces, with potentially different
> sizes of address bus wired up to each. It's also a conceptually-wrong
> approach anyway, since this isn't a property of the SMMU; it's a property of
> the interconnect(s) upstream of the SMMU.
> 
> IIRC you were working on Tegra - if so, Thierry already has a plan, see this
> thread:
> https://lore.kernel.org/linux-arm-kernel/20190930133510.GA1904140@ulmo/

Thanks for the reply and link!