| Message ID | 20191015212004.24748-2-mike.leach@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | coresight: etm4x: Fixes and updates for sysfs API | expand |
Hi Mike, On Tue, Oct 15, 2019 at 10:19:54PM +0100, Mike Leach wrote: > ETMv4.4 adds in support for tracing secure EL2 (per arch 8.x updates). > Patch accounts for this new capability. > > Reviewed-by: Leo Yan <leo.yan@linaro.org> > Signed-off-by: Mike Leach <mike.leach@linaro.org> > --- > .../hwtracing/coresight/coresight-etm4x-sysfs.c | 12 ++++++------ > drivers/hwtracing/coresight/coresight-etm4x.c | 5 ++++- > drivers/hwtracing/coresight/coresight-etm4x.h | 15 +++++++++++---- > 3 files changed, 21 insertions(+), 11 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > index 219c10eb752c..b6984be0c515 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > @@ -738,7 +738,7 @@ static ssize_t s_exlevel_vinst_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - val = BMVAL(config->vinst_ctrl, 16, 19); > + val = (config->vinst_ctrl & ETM_EXLEVEL_S_VICTLR_MASK) >> 16; > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -754,8 +754,8 @@ static ssize_t s_exlevel_vinst_store(struct device *dev, > return -EINVAL; > > spin_lock(&drvdata->spinlock); > - /* clear all EXLEVEL_S bits (bit[18] is never implemented) */ > - config->vinst_ctrl &= ~(BIT(16) | BIT(17) | BIT(19)); > + /* clear all EXLEVEL_S bits */ > + config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK); > /* enable instruction tracing for corresponding exception level */ > val &= drvdata->s_ex_level; > config->vinst_ctrl |= (val << 16); > @@ -773,7 +773,7 @@ static ssize_t ns_exlevel_vinst_show(struct device *dev, > struct etmv4_config *config = &drvdata->config; > > /* EXLEVEL_NS, bits[23:20] */ > - val = BMVAL(config->vinst_ctrl, 20, 23); > + val = (config->vinst_ctrl & ETM_EXLEVEL_NS_VICTLR_MASK) >> 20; > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -789,8 +789,8 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev, > return -EINVAL; > > spin_lock(&drvdata->spinlock); > - /* clear EXLEVEL_NS bits (bit[23] is never implemented */ > - config->vinst_ctrl &= ~(BIT(20) | BIT(21) | BIT(22)); > + /* clear EXLEVEL_NS bits */ > + config->vinst_ctrl &= ~(ETM_EXLEVEL_NS_VICTLR_MASK); > /* enable instruction tracing for corresponding exception level */ > val &= drvdata->ns_ex_level; > config->vinst_ctrl |= (val << 20); > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c > index 8f98701cadc5..efe120925f9d 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > @@ -648,6 +648,7 @@ static void etm4_init_arch_data(void *info) > * TRCARCHMAJ, bits[11:8] architecture major versin number > */ > drvdata->arch = BMVAL(etmidr1, 4, 11); > + drvdata->config.arch = drvdata->arch; > > /* maximum size of resources */ > etmidr2 = readl_relaxed(drvdata->base + TRCIDR2); > @@ -799,6 +800,7 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config) > static u64 etm4_get_access_type(struct etmv4_config *config) > { > u64 access_type = etm4_get_ns_access_type(config); > + u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0; > > /* > * EXLEVEL_S, bits[11:8], don't trace anything happening > @@ -806,7 +808,8 @@ static u64 etm4_get_access_type(struct etmv4_config *config) > */ > access_type |= (ETM_EXLEVEL_S_APP | > ETM_EXLEVEL_S_OS | > - ETM_EXLEVEL_S_HYP); > + s_hyp | > + ETM_EXLEVEL_S_MON); > > return access_type; > } > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 546d790cb01b..b873df38e7d8 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -181,17 +181,22 @@ > /* PowerDown Control Register bits */ > #define TRCPDCR_PU BIT(3) > > -/* secure state access levels */ > +/* secure state access levels - TRCACATRn */ > #define ETM_EXLEVEL_S_APP BIT(8) > #define ETM_EXLEVEL_S_OS BIT(9) > -#define ETM_EXLEVEL_S_NA BIT(10) > -#define ETM_EXLEVEL_S_HYP BIT(11) > -/* non-secure state access levels */ > +#define ETM_EXLEVEL_S_HYP BIT(10) > +#define ETM_EXLEVEL_S_MON BIT(11) > +/* non-secure state access levels - TRCACATRn */ > #define ETM_EXLEVEL_NS_APP BIT(12) > #define ETM_EXLEVEL_NS_OS BIT(13) > #define ETM_EXLEVEL_NS_HYP BIT(14) > #define ETM_EXLEVEL_NS_NA BIT(15) > > +/* secure / non secure masks - TRCVICTLR, IDR3 */ > +#define ETM_EXLEVEL_S_VICTLR_MASK GENMASK(19, 16) > +/* NS MON (EL3) mode never implemented */ > +#define ETM_EXLEVEL_NS_VICTLR_MASK GENMASK(22, 20) > + > /** > * struct etmv4_config - configuration information related to an ETMv4 > * @mode: Controls various modes supported by this ETM. > @@ -238,6 +243,7 @@ > * @vmid_mask0: VM ID comparator mask for comparator 0-3. > * @vmid_mask1: VM ID comparator mask for comparator 4-7. > * @ext_inp: External input selection. > + * @arch: ETM architecture version (for arch dependent config). > */ > struct etmv4_config { > u32 mode; > @@ -280,6 +286,7 @@ struct etmv4_config { > u32 vmid_mask0; > u32 vmid_mask1; > u32 ext_inp; > + u8 arch; > }; I am applying this patch, no need to send it again. > > /** > -- > 2.17.1 >
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 219c10eb752c..b6984be0c515 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -738,7 +738,7 @@ static ssize_t s_exlevel_vinst_show(struct device *dev, struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etmv4_config *config = &drvdata->config; - val = BMVAL(config->vinst_ctrl, 16, 19); + val = (config->vinst_ctrl & ETM_EXLEVEL_S_VICTLR_MASK) >> 16; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } @@ -754,8 +754,8 @@ static ssize_t s_exlevel_vinst_store(struct device *dev, return -EINVAL; spin_lock(&drvdata->spinlock); - /* clear all EXLEVEL_S bits (bit[18] is never implemented) */ - config->vinst_ctrl &= ~(BIT(16) | BIT(17) | BIT(19)); + /* clear all EXLEVEL_S bits */ + config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK); /* enable instruction tracing for corresponding exception level */ val &= drvdata->s_ex_level; config->vinst_ctrl |= (val << 16); @@ -773,7 +773,7 @@ static ssize_t ns_exlevel_vinst_show(struct device *dev, struct etmv4_config *config = &drvdata->config; /* EXLEVEL_NS, bits[23:20] */ - val = BMVAL(config->vinst_ctrl, 20, 23); + val = (config->vinst_ctrl & ETM_EXLEVEL_NS_VICTLR_MASK) >> 20; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } @@ -789,8 +789,8 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev, return -EINVAL; spin_lock(&drvdata->spinlock); - /* clear EXLEVEL_NS bits (bit[23] is never implemented */ - config->vinst_ctrl &= ~(BIT(20) | BIT(21) | BIT(22)); + /* clear EXLEVEL_NS bits */ + config->vinst_ctrl &= ~(ETM_EXLEVEL_NS_VICTLR_MASK); /* enable instruction tracing for corresponding exception level */ val &= drvdata->ns_ex_level; config->vinst_ctrl |= (val << 20); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 8f98701cadc5..efe120925f9d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -648,6 +648,7 @@ static void etm4_init_arch_data(void *info) * TRCARCHMAJ, bits[11:8] architecture major versin number */ drvdata->arch = BMVAL(etmidr1, 4, 11); + drvdata->config.arch = drvdata->arch; /* maximum size of resources */ etmidr2 = readl_relaxed(drvdata->base + TRCIDR2); @@ -799,6 +800,7 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config) static u64 etm4_get_access_type(struct etmv4_config *config) { u64 access_type = etm4_get_ns_access_type(config); + u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0; /* * EXLEVEL_S, bits[11:8], don't trace anything happening @@ -806,7 +808,8 @@ static u64 etm4_get_access_type(struct etmv4_config *config) */ access_type |= (ETM_EXLEVEL_S_APP | ETM_EXLEVEL_S_OS | - ETM_EXLEVEL_S_HYP); + s_hyp | + ETM_EXLEVEL_S_MON); return access_type; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 546d790cb01b..b873df38e7d8 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -181,17 +181,22 @@ /* PowerDown Control Register bits */ #define TRCPDCR_PU BIT(3) -/* secure state access levels */ +/* secure state access levels - TRCACATRn */ #define ETM_EXLEVEL_S_APP BIT(8) #define ETM_EXLEVEL_S_OS BIT(9) -#define ETM_EXLEVEL_S_NA BIT(10) -#define ETM_EXLEVEL_S_HYP BIT(11) -/* non-secure state access levels */ +#define ETM_EXLEVEL_S_HYP BIT(10) +#define ETM_EXLEVEL_S_MON BIT(11) +/* non-secure state access levels - TRCACATRn */ #define ETM_EXLEVEL_NS_APP BIT(12) #define ETM_EXLEVEL_NS_OS BIT(13) #define ETM_EXLEVEL_NS_HYP BIT(14) #define ETM_EXLEVEL_NS_NA BIT(15) +/* secure / non secure masks - TRCVICTLR, IDR3 */ +#define ETM_EXLEVEL_S_VICTLR_MASK GENMASK(19, 16) +/* NS MON (EL3) mode never implemented */ +#define ETM_EXLEVEL_NS_VICTLR_MASK GENMASK(22, 20) + /** * struct etmv4_config - configuration information related to an ETMv4 * @mode: Controls various modes supported by this ETM. @@ -238,6 +243,7 @@ * @vmid_mask0: VM ID comparator mask for comparator 0-3. * @vmid_mask1: VM ID comparator mask for comparator 4-7. * @ext_inp: External input selection. + * @arch: ETM architecture version (for arch dependent config). */ struct etmv4_config { u32 mode; @@ -280,6 +286,7 @@ struct etmv4_config { u32 vmid_mask0; u32 vmid_mask1; u32 ext_inp; + u8 arch; }; /**